修订2014年9月3日

This manual applies to REV D of the board.

FPGA夹层卡高清多媒体接口（FMC-HDMI）外围板使开发人员能够将HDMI输入端口添加到基于现场的可编程门阵列（FPGA）系统中。FMC-HDMI为客户提供了一个开发平台，以利用与图像处理应用程序一起使用的高清图像捕获。

Features include:

• (2x) HDMI Type A Receptacles
• HDMI接收器（ADV7611）
• HDMI Buffer (AD8195)
• 板载EdidEEPROM
• Male FMC LPC connector for digital signals
• Compatible with a wide range of VADJ voltages (1.8V – 3.3V)

The FMC-HDMI card contains two HDMI input ports. The first port, HDMI1, contains an ADI ADV7611 Receiver and outputs a decoded, level translated digital video signal to the FMC connector. The second port, HDMI2, contains an ADI AD8195 Buffer and outputs an HDMI-encoded signal to the FMC connector, leaving the system board to decode the signal (either in the FPGA or an external receiver).

HDMI端口的适当性完全取决于应用程序。例如，尽管HDMI2没有解码信号，但它输出到较小数量的引脚（14而不是36），这在输入可用性有限的设计中很有用。由于必须在连接的系统板上进行解码，因此电路必须支持TMD的HDMI-type信号。例如，Xilinx®FPGA家庭支持3.3V供电的I/O银行中的TMDS_33输入标准。

An Analog Devices ADV7611 Receiver decodes the signal on HDMI1. This low power, 165MHzreceiver supports formats up to UXGA 60Hz at 8 bit at 161MHz。它已在Wuxga（1080p）60Hz的148.5测试MHz。The receiver provides an audio output port for audio extracted from the HDMI signal in the following formats: I2S, S/PDIF, and Direct Stream Transfer (DST). It also features an advanced mute controller.

The ADV7611 Receiver contains several other features, such as a CEC 1.4-compatible controller for consumer device remote control and discovery and EDID (Extended Display Identification Data)内存。

Note: For more information on the ADV7611, see ADI datasheets and User Guide available online at:http://www.analog.com/ADV7611

Below are the pin-outs from the ADV7611 Receiver and other HDMI1 port signals to the FMC connector:

Table 1. HDMI1-FMC pin mapping

The ADV7611 is configured and controlled via an I2C interface, which is accessible through the HDMI1SDA and HDMI1SCL pins on the FMC connector. The ADV7611 User Guide specifically describes the different registers and commands necessary to control the Receiver.

所有音频和视频信号上都有级别的翻译器，它们可以升级为1.8V，2.5V和3.3V。所需的水平由VADJ电压级别设置。

AD8195是具有均衡的TMD输入的HDMI缓冲液，并且可以选择预先强调的TMDS输出。AD8195包括用于DDC总线的双向缓冲，以及带有CEC总线的集成上拉电阻的双向缓冲。DDC和CEC缓冲液独立于TMDS缓冲液供电，因此在系统电动机电源时可以保持DDC/CEC功能。

An on-board pre-programmedEEPROMis connected to the DDC (Display Data Channel) bus of the HDMI2 port. The following EDID (Extended Display Identification Data) is programmed in the factory:

表2。EEPROM预编程的内容。

TheEEPROMcan be freely re-written through the J4 header holes and 6-pin Pmod cable. DuringEEPROM编程，力量EEPROM由J4的引脚6提供，因此请确保没有HDMI电缆同时插入。

以下是从AD8195缓冲区和其他HDMI2端口信号到FMC连接器的引脚输出：

表3. HDMI2-FMC引脚映射。

WARNING: VADJ must be 3.3V to properly use the buffer on HDMI2. The TX_EN pin is held low by default, so the buffer is disabled on power-up. With the buffer disabled, VADJ can be in the range of (1.8V-3.3V).

Note: For more information on the AD8195, see ADI datasheets available online athttp://www.analog.com/AD8195

FMC-HDMI使用SAMTEC ASP-134604-01低针计数男性连接器作为数字信号的主要连接器。董事会完全符合Vita 57.1规格。该连接器支持1.8V-3.3V银行电源电压（VADJ）的全部范围。

I²C充当IPMIEEPROM, providing hardware definition information. For more information, consult the VITA 57.1 specs.

Issue #1: The on-board FMCEEPROMcontents do not conform to the VITA 57.1 FPGA Mezzanine Card (FMC) Standard and the IPMI Platform Management FRU Information Storage Specifications.

Affected systems: Management software that read and rely on FRU data for some functionality.

Impact: minor.

Solution: Use the publishedFMC-HDMI-frufixproject, created in Vivado 2016.4 and targeting the Digilent Zedboard, to reprogram theEEPROMwith the correct image. The project can also be adapted to any other Xilinx FPGA board available.