Getting Started with Digilent Pmod IPs

Digilent provides several IPs that are designed to make implementing and using a Pmod on an FPGA as straightforward as possible. This guide will describe how to use a Pmod IP core in Vivado Microblaze or Zynq design.

At the end of this tutorial you will have a Vivado design and demo for your FPGA or Zynq platform that uses a Digilent Pmod IP core.

以下两个下拉列表显示了本教程支持哪些Digilent FPGA系统板和PMOD，以及有关每个教程需要知道的每个详细信息才能完成本教程。

支持平台

Platform	Processor Type
Arty A7	Microblaze
Arty S7	Microblaze
Arty Z7	Zynq
Basys3	Microblaze
CMOD A7	Microblaze
Cmod S7	Microblaze
Cora Z7	Zynq
Genesys2	Microblaze
Nexys4	Microblaze
Nexys4-DDR	Microblaze
Nexys Video	Microblaze
剑	Microblaze
Zybo	Zynq
ZyboZ7	Zynq

PMODs Supported

PMOD	接口类型	Reference clock frequency (MHz）	Reference Clock signal name	Interrupt pin name/s	使用PMODGPIO	补充说明
8ld	GPIO	-	-	-	Yes	-
ACL	SPI	80	ext_spi_clk	-	-	-
ACL2	SPI	50	ext_spi_clk	-	-	-
AD1	SPI	-	-	-	-	-
AD2	IIC	-	-	-	-	-
AD5	SPI	50	-	-	-	-
ALS	SPI	50	ext_spi_clk	-	-	-
AMP2	GPIO	-	-	timer_interrupt	-	-
AQS	IIC	-	-	-	-	-
BB	GPIO	-	-	-	Yes	-
BLE	UART	-	-	-	-	-
BT2	UART	-	-	-	-	-
BTN	GPIO	-	-	-	Yes	-
能够	SPI	100	ext_spi_clk	spi_interruptGPIO_interrupt		-
CLS	SPI	50	ext_spi_clk	-	-	-
CMPS2	IIC	-	-	-	-	SDK project requires math library
颜色	IIC	-	-	-	-	-
DA1	SPI	50	ext_spi_clk	-	-	-
DHB1	PWM/GPIO	-	-	-	-	-
DPG1	SPI	50	ext_spi_clk	-	-	-
enc	GPIO	-	-	-	-	-
ESP32	UART	-	-	-	-	-
全球定位系统	UART	-	-	gps_uart_interrupt	-	-
GYRO	SPI	50	ext_spi_clk	-	-	-
HYGRO	IIC	-	-	-	-	-
JSTK	SPI	16	ext_spi_clk	-	-	-
JSTK2	SPI	16	ext_spi_clk	-	-	-
KYPD	GPIO	-	-	-	-	-
LED	GPIO	-	-	-	Yes	-
MAXSONAR	GPIO	-	-	-	-	-
MicroSD	使用PMOD SD IP核心					-
MTD	SPI	-	-	-	-	-
导航	spi/GPIO	50	ext_spi_clk	-	-	-
OLED	spi/GPIO	-	-	-	-	-
Oledrgb	spi/GPIO	50	ext_spi_clk	-	-	-
PIR	GPIO	-	-	-	-	-
R2R	GPIO	-	-	-	-	-
RTCC	IIC	-	-	-	-	-
SD	SPI	-	-	-	-	-
SF3	SPI	50	ext_spi_clk	QSPI_INTERRUPT	-	-
SSR	GPIO	-	-	-	Yes	-
SWT	GPIO	-	-	-	Yes	-
TC1	SPI	50	ext_spi_clk	-	-
TMP3	IIC	-	-	-	-
WIFI	SPI	-	-	wf_interrupt	-	Need 385 KB of BRAM or DDR

• 支持的Digilent 7系FPGA系统板
• MicroUSB Cable/s
• 一个或多个支持的数字PMODS

• Xilinx Vivado 2018.2 with Xilinx SDK and Digilent Board Files
  • 其他版本的Vivado可能会起作用，但不能保证功能
  • 看到"Installing Vivado and Digilent Board Files"教程for more information.
• Digilent Vivado IP Library
  • 第2步本教程涵盖了如何下载和提取这些文件。

要确定您是否需要使用Microblaze或Zynq进行本教程，请参阅该条目支持平台dropdown table found in theOverview Section本教程。或者，导航到您的平台资源中心这里。

Microblaze

Follow theGetting Started with Vivado IP Integrator教程以获得基本的微封闭块设计。



An example of a MicroBlaze block design for a board that has external DDR memory.

Zynq

Follow theGetting Started with Vivado IP Integrator教程to obtain a basic Zynq block design.



An example of a Zynq block design.

2.1) Find the latest release of Digilent'svivado-libraryrepository where the version number matches the version of Vivado being used (example: “v2016.4-1” is the first release for Vivado 2016.4). Download thevivado-library-.zipfile (不是源代码档案之一！），然后在令人难忘的位置提取此存档。该GITHUB存储库包含大量旨在与Digilent板一起使用的IP内核，包括Digilent的所有PMOD IP内核和PMOD接口描述。

2.2）单击Project Settings在项目经理下。

2.3) ClickIP然后打开Repository Managertab. Click the 添加button and select thevivado-libraryfolder from where the ZIP archive was extracted to. ClickOK。

3.1）单击木板tab (Highlighted in orange below)

3.2) Scroll down to the Pmod section of the board components. Double click the connector that you want to set up.

3.3）为您的特定PMOD选择PMOD IP，然后单击OK。The photo below shows the IP core for PmodOLEDrgb being selected.

4.1) ClickRun Connection Automationthen check the box next to the name of your Pmod IP core and clickOK。

将参考时钟附加到PMOD IP核心是不同的，具体取决于您使用的平台。选择最能描述您平台的选项卡（请在“Overview Sectionif you don't know).

Zynq

5.1) Double click theZYNQ Processing System块重新定制它。在左侧的菜单中，单击Clock Configuration。扩展PL织物时钟drop down and check the first FCLK_CLK that is not already checked to activate it. Set the requested frequency to the frequency required for your Pmod. This frequency can be found in the Pmod compatibility chart in theOverview Section本教程。点击OK。

小费

如果其中一个FCLK_CLK已经检查has a frequency that matches the frequency needed for your pmod, you may use that clock. It is possible to connect a single clock to multiple destinations.

5.2) Connect this new clock to the clock input on your Pmod IP Core. The name of the clock input for your Pmod IP core can be found in the Pmod compatibility chart in theOverview Section本教程。

MicroBlaze with MIG

5.1) Double click the mig_7series block to re-customize it. In the Xilinx Memory Interface Generator window, keep clickingNextuntil you seeSelect Additional Clocks（如下所示）。单击此框，然后选择PMOD所需的频率或最接近可用的较慢频率。所需频率可以在PMOD兼容性图表中找到Overview Section本教程。

小费

如果已经使用了另一个时钟，并且具有与PMOD所需的频率相匹配的频率，则可以使用该时钟。可以将单个时钟连接到多个目的地。如果是这种情况，您可以Cancelout of the MIG configuration dialog.

5.2）继续点击Next。当您到达PIN选择屏幕时，请单击Validateand thenOK。继续点击Next。点击Accept在许可协议屏幕上，然后继续点击Next。到达结束后，请单击Generate用其他时钟再生MIG块。

5.3）将此新时钟连接到PMOD IP核心上的时钟输入。您的PMOD IP核心的时钟输入端口的名称可以在PMOD兼容性图表中找到Overview Section本教程。

无MIG的微型闪电

5.1) Double click the clocking wizard IP block to re-customize it. In the customization dialog, select the Output Clocks tab. Check the next clock that is not already checked to activate it. Set the requested output frequency to the frequency required for your Pmod. This frequency can be found in the Pmod compatibility chart in theOverview Section本教程。点击OK。

小费

如果已经使用了另一个时钟，并且具有与PMOD所需的频率相匹配的频率，则可以使用该时钟。可以将单个时钟连接到多个目的地。

5.2) Connect this new clock to the clock input on your Pmod IP Core. The name of the clock input for your Pmod IP core can be found in the Pmod compatibility chart in theOverview Section本教程。

附加一个Pmod IP核心processo中断r is different depending on which platform you are using. Select the tab that describes your platform best (consult the platform compatibility table in theOverview Sectionif you don't know).

Zynq

6.1）如果一个端口命名IRQ_F2Pdoes not exist on your Zynq Processing System block, double click on the block to re-customize it. In the menu to the left, clickInterrupts。Check and then expand Fabric Interrupts, then expandPL-PS Interrupts并选中IRQ_F2P旁边的框。

6.2）添加一个concatIP核心到块设计。重新定制Concat块，以确保输入数量匹配您需要连接到Zynq处理器的中断数量 - 可能只有一个。点击Ok。

6.3）将您的PMOD IP Core的中断端口连接到输入端口，并将Concat的输出端口和Concat的输出端口IRQ_F2P port of your Zynq Processing System.

Microblaze

6.1）如果您的Microblaze块没有连接到其中断端口的AXI中断控制器，请在块设计中添加AXI中断器。手动将AXI_INTC_0的中断端口连接到微封闭块的中断端口。利用连接自动化to connect it's AXI interface to the rest of the system.

6.2）添加一个concatIP核心到块设计。Re-customize the concat block to make sure that the number of inputs matches the number of interrupts you need to connect to your Microblaze Processor - probably only one. ClickOk。

6.3）将您的PMOD IP Core的中断端口连接到输入端口，并将Concat的输出端口和Concat的输出端口intr您的Axi中断控制器的端口。

7.1) Click the Regenerate Layout按钮重新排列您的块设计。

7.2）选择 Validate Design。这将检查设计和连接错误。

7.3) If you have already created an HDL wrapper for your block design as part of the board specificGetting Started With…教程，跳过此步骤的其余部分。否则，在设计验证步骤之后，我们将继续创建HDL系统包装器。单击Sourcestab and find your block design.

7.4) Right click on your block design and clickCreate HDL Wrapper。Let Vivado manage the wrapper and automatically update it and clickOK。



This will create a top module in VHDL and will allow you to generate a bitstream.

8.1) In the top toolbar in Vivado, click Generate Bitstream。This can also be found in theFlow Navigatorpanel on the left, underProgram and Debug。If you haven't already saved your design, you will get a prompt to save the block design.

8.2) The bit file generation will begin. The tool will run合成andImplementation。After both have been successfully completed, the bit file will be created. You will find a status bar of Synthesis and Implementation running on the top right corner of the project window.

这个过程可能需要5至60分钟根据计算机的不同，Vivado正在运行和目标FPGA的大小。

8.3) After the bitstream has been generated, a message prompt will pop-up on the screen. You don't have to open the Implemented Design for this demo. Just clickCancel。

9.1) At the top of the Vivado window, clickFile → Export → Export Hardware。Check the box to包括Bitstreamand clickOK。这将为Xilinx SDK提供有关硬件设计所需的所有信息，以及将硬件编程到目标FPGA系统板上所需的文件。



将在项目目录中创建一个新的文件目录echo_server.SDKsimilar to the Vivado hardware design project name. Two other files,.sysdefand.hdf也是创建的。此步骤本质上创建了一个新的SDK工作区。

9.2）在主工具栏上，单击文件→启动SDK。将两个下拉菜单作为默认<本地项目>and clickOK。This will open Xilinx SDK and import the exported hardware.

The HW design specification and included IP blocks are displayed in the “system.hdf” file. Xilinx SDK is independent of Vivado, i.e. from this point, you can create your SW project in C/C++ on top of the exported HW design. If necessary, SDK can be launched directly with the .sdk folder in the main Vivado project directory as the workspace. From this point, if you need to go back to Vivado and make changes to the HW design, then it is recommended to close the SDK window and make the required HW design edits in Vivado. After this you must follow the sequence of saving design, allowing Vivado to regenerate the HDL wrapper, and generating a new bit file. This new bit file and modified hardware design must then be exported to SDK.

在Project Explorer左侧的标签，您可以看到硬件平台项目。硬件平台的名称遵循Vivado创建的块设计包装器的名称。该硬件平台具有所有HW设计定义，已添加的IP接口，外部输出信号信息和本地内存地址信息。

The drivers for any Pmod IPs in the design can be found in the appropriate folder in the hardware platform, under/drivers。If you want to edit these drivers, use the versions found in the board support package project underlibsrc/。If you do modify the drivers, keep in mind that any changes to your hardware will overwrite these changes, as well as any use of theRegenerate BSP Sources选项。

11.1) Click the Newdropdown arrow and select申请项目。



给您的项目一个没有空的空间的名称，然后单击Next。

11.2) SelectEmpty Applicationfrom the list of templates and clickOK。

You will see two new folders in theProject Explorerpanel.

• Your application project which contains all the binaries, .C and .H (Header) files
• The board support package for your project, which contains driver source files that your project may include

我们的主要工作源文件夹还包含此处显示的重要文件，即“ lscript.ld”。这是一个Xilinx自动生成的链接脚本文件，包括有关块设计不同IP组件的内存地址以及其他内存区域的尺寸的信息。

扩展design_1_wrapper_platform_0文件夹。在driversfolder, you will find the list of Pmods that you are using in your design. Expand thePMOD…/examplesfolder and copy all of the files found here into theproject_name/src文件夹。

13.1）确保使用Micro USB电缆打开并连接到主机PC，用于UART和编程。在某些板上，您只需要连接一个ProG/UART端口，而在其他板上，您需要将PC连接到通常名为UART和PROG或JTAG的两个不同端口。在顶部工具栏上，单击 Program FPGA按钮。一些板还将要求它们连接到单独的电源。

13.2）单击Programto program your FPGA with your hardware design.

14.1）大多数演示要求您在PC上使用串行终端读取演示打印的消息。终端的设置将根据您的板子而有所不同，但通常您需要使用115200或9600，8位数据，没有奇偶校验和一个停止位的波特率。Zynq项目将使用115200 BAUD，而微型封面项目的波特率将取决于Vivado的Uartlite IP的配置。

14.2）选择您的应用程序项目，然后单击 Run As…按钮。Select在硬件（系统调试器）上启动and clickOK。

14.3）Xilinx SDK将在Main.C上运行该程序。查看示例主文件顶部的评论标头，以获取有关演示的功能以及任何其他设置要求的更多信息。