This is the landing page for all of the Verilog based projects. It's clearly still a work in progress, but more tutorials and links will be added as they are created.

For now, you can view the list of projects listed statically below:

• Apseudo Project 0for those wanting to learn how to navigate Vivado in general.
• Project 1for learning the major keywords and concepts.
• Project 2for programming an FPGA for the first time.

A list of some other potentially useful resources is available below:

• Guide to Installing Vivado
• What is an XDC fileand how does it interface with my Vivado code