Arty A7 XADC Demo

这个简单的XADC演示项目展示了Arty A7的XADC引脚功能的简单用法。行为如下：

• 随着所选XADC引脚的电压差变大，8个用户LED从右上到左到左至右侧的递增。
• 四个开关选择要从哪个通道读取。

• Arty A7 with a MicroUSB Programming Cable
• Vivado installation compatible with the latest release of this demo (2022.1)
  • SeeInstalling Vivado, Vitis, and Digilent Board Files用于安装说明。
• Wires and a circuit to measure

First and foremost, releases - consisting of a set of files for download - are only compatible with a specific version of the Xilinx tools, as specified in the name of the release (referred to as arelease tag）。此外，发布仅与板的指定变体兼容。例如，Zybo Z7标记为“ 20/DMA/2020.1”的版本仅适用于板的-20变体和Vivado 2020.1。

The latest release version for this demo is highlighted in green.

Note:从2020.1之前释放FPGA演示，使用了不同的GIT结构，并使用了不同的释放标签命名方案。

Note for Advanced Users:All demos for the Arty A7 are provided through theArty-A7repository on Github. Further documentation on the structure of this repository can be found on this wiki'sDigilent FPGA演示GIT存储库页。

有关使用最新版本的说明可以在此下拉列表中找到：

使用最新版本

Note:在许多Digilent FPGA演示中，此工作流程很常见。屏幕截图可能与您正在使用的演示不符。

重要的：These steps are only to be used with releases for Xilinx tools versions 2020.1 and newer. Older releases may require other flows, as noted in the table of releases.

首先，从上面链接的演示发布页面下载并提取“*.xpr.zip”文件。

---

Open a Vivado Project from a Release

Launch Vivado

选择相对应的下拉to your operating system, below.

视窗

Open Vivado through the start menu or desktop shortcut created during the installation process.

Linux

打开终端，然后将目录（CD）更改为可以放置Vivado会话的日志文件的文件夹，然后运行以下命令：

source /Vivado//settings64.sh vivado

---

In Vivado's welcome screen, use theOpen Projectbutton to navigate to and open the XPR file contained in the folder the release was extracted into.

---

建立一个Vivado项目

请注意，如果您的项目已经具有生成的bitstream，如窗口右上角所示的状态所示，读取“ write_bitstream完整！”，则可以跳过本节。

Generate a Bitstream

为了创建可用于编程目标板的文件，需要运行“编译管道”的每个阶段。

This starts withSynthesis。综合创建了逻辑门的描述，并在XDC文件中包含的约束下执行HDL文件所描述的功能所需的连接。要运行合成单击在里面toolbar or在里面Flow Navigator。The output of Synthesis is then passed to Implementation.

执行有几个步骤。始终运行的步骤是选择设计(Optimize the design to fit on the target FPGA),位置设计(Lay out the design in the target FPGA fabric), andRoute Design(Route signals through the fabric). To run Implementation click either在里面toolbar or在里面Flow Navigator。然后将此输出传递到Bitstream Generator。

TheBitstream Generatorgenerates the final output file needed for programming the FPGA. To run Bitstream Generation click either在里面toolbar or在里面Flow Navigator。With no settings changed, the generator will create a '.bit' file.

Depending on the complexity of the design, the board used, and the strength of your computer, the process of building the project can take between 5 and 60 minutes. When complete, a pop up dialog will appear, prompting you to select one of several options. None are relevant for the purposes of this guide, so click取消。The “write_bitstream complete” status message can be seen in the top right corner of the window, indicating that the demo is ready to be deployed to your board.

---

设置Arty A7

将MicroUSB编程电缆插入Arty A7的Prog/UART端口中。设置您的电路。在我们的情况下，我们使用了由8 1k欧姆电阻组成的电阻梯子。

---

Program a Bitstream onto an FPGA Board

可以通过单击可以打开Vivado的硬件管理器Open Hardware Manager在Vivado窗口左侧的流导航器窗格的底部。

编程设备的第一步是将Vivado硬件服务器连接到目标。到达打开硬件目标wizard click the在窗户顶部附近的绿色横幅中链接。从打开的下拉下，选择。

向导打开后，单击下一个。

---

The next screen asks if the hardware server is local or remote. If the board is connected to the host computer choose local, if it is connected to another machine choose remote and fill in the主机名和Portfields.

Click下一个接着说。

---

此屏幕提供了连接到硬件服务器的设备列表。如果只有一个连接，它将是显示的唯一设备。

Click下一个接着说。

---

The final screen shows a summary of the options selected in the wizard. Verify the information and click结束。板现在已连接到硬件服务器。

---

To program the device with the bit file generated earlier, either click thelink in thegreen bannerat the top of the window or click thebutton in theFlow Navigatorunder。从打开的下拉下，选择the device to program (Example:) and the following window will open:

TheBitstream文件字段应自动填写，并在前面生成的位文件填充。如果没有，请单击按钮位于字段的右端，导航到
/.runs/impl_1/并选择位文件（示例：）。Now clickProgram。这将连接到板，清除当前配置，并使用新的位文件进行编程。

---

此时，该演示现在正在您的董事会上运行。参考描述和功能sections of this document for more information on what it does.

For this demo, A0-A5 are single ended analog pins while A6-A7, A8-A9, and A10-A11 are differential ports.

LED从右向左打开，然后随着输入电压的增加而在底部缠绕。

To display a different channel on the display and LEDs, change the user switches to the desired channel, as seen in the table below.

All materials related to the use of the Arty A7 can be found on itsResource Center。

有关在Vivado创建简单HDL项目的过程的演练，请参阅开始使用仅硬件设计的Vivado。Information on important parts of theGUI, and indirect discussion of the steps required to modify, rebuild, and run this demo in hardware can also be found here.

要获得技术支持，请访问FPGADigilent论坛的部分。