Zybo Z7XADC Demo

This simple XADC demo is a Verilog project made to demonstrate usage of the Analog to Digital Converter hardware present within the Zybo Z7's Zynq chip.

• XADC IP核心用于读取XADC PMOD端口的四个垂直销钉 - 通道的垂直对的电压差。
• 这LEDassociated with a channel brightens as that channel's voltage increases.

• 带有MICUSB编程电缆的Zybo Z7
• Vivado installation compatible with the latest release of this demo (2020.1)
  • 看安装Vivado，Vitis和Digilent板文件安装说明。
• A circuit to measure

首先，首先，发布的版本 - 由一组文件组成 - 仅与Xilinx工具的特定版本兼容，如发行版的名称所指定（称为一个称为一个释放标签）。In addition, releases are only compatible with the specified variant of the board. For example, a release tagged “20/DMA/2020.1” for the Zybo Z7 is only to be used with the -20 variant of the board and Vivado 2020.1.

该演示的最新版本以绿色突出显示。

笔记：Releases for FPGA demos from before 2020.1 used a different git structure, and used a different release tag naming scheme.

注明高级用户：All demos for the Zybo Z7 are provided through theZybo-Z7github上的存储库。有关此存储库结构的进一步文档可以在此Wiki上找到数字FPGADemo Git Repositories页。

Instructions on the use of the latest release can be found in this dropdown:

Using the Latest Release

笔记：This workflow is common across many Digilent FPGA demos. Screenshots may not match the demo you are working with.

重要的:这些步骤仅适用于Xilinx工具版本2020.1和更新的版本。旧版本可能需要其他流，如发行表中所述。

First, download and extract the '*.xpr.zip' file from the demo release page, linked above.

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从发行版开设一个Vivado项目

启动Vivado

在下面选择与您的操作系统相对应的下拉菜单。

Windows

通过在安装过程中创建的“开始”菜单或桌面快捷方式打开Vivado。

Linux

打开终端，然后将目录（CD）更改为可以放置Vivado会话的日志文件的文件夹，然后运行以下命令：

源/vivado/<版本>/settings64.sh vivado

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在Vivado的欢迎屏幕上，请使用开放项目按钮要导航到并打开文件夹中包含的XPR文件，将发布已提取为。

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Build a Vivado Project

Note that if your project already has a generated bitstream, as indicated by the status in the top right corner of the window reading “write_bitstream Complete!”, then you can skip this section.

生成一个bitstream

In order to create a file that can be used to program the target board, each stage of the “compilation pipeline” needs to be run.

这是从合成。合成creates a description of the logic gates and connections between them required to perform the functionality described by the HDL files, given the constraints included in XDC files. To run Synthesis click either在工具栏或in the流导航器。然后，合成的输出将传递给实施。

Implementationhas several steps. The steps that are always run are选择设计（优化设计以适合目标FPGA），Place Design（在目标FPGA织物中布置设计）和路线设计（路由信号通过织物）。要运行实施，请单击在工具栏或in the流导航器。This output is then passed on to the Bitstream Generator.

这Bitstream Generator生成编程FPGA所需的最终输出文件。要运行bitstream生成，请单击在工具栏或in the流导航器。没有更改设置，生成器将创建一个“ .bit”文件。

根据设计的复杂性，使用的板和计算机的强度，构建项目的过程可能需要5到60分钟。完成后，将出现一个弹出对话框，提示您选择几个选项之一。与本指南的目的无关，因此请单击Cancel。可以在窗口的右上角看到“ write_bitstream完整”状态消息，表明该演示已准备好部署到板上。

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Set up the Zybo Z7

In order to use the demo, you will need to connect a circuit to the XADC Pmod Port in order to measure a voltage. The following example shows a voltage divider that produces each voltage between 0 V and 1 V in increments of 0.33 V. This circuit uses a chain of three 1 kΩ resistors in series with a 4.7 kΩ and a 2.2 kΩ resistor. The circuit is tied to the 3V3 andgndXADC PMOD标头的引脚提供电源。XADC端口的下排的每个n'引脚都连接到地面。

重要的

要测量的电压应在0到1.0伏的范围内。

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将bitstream编程到FPGA板上

Vivado's Hardware Manager can be opened by clicking on打开硬件管理器at the bottom of the Flow Navigator pane on the left side of the Vivado window.

这first step to programming a device is to connect the Vivado Hardware Server to it as a target. To get to theOpen Hardware Target向导单击链接绿色横幅near the top of the window. From the drop-down that opens, select。

Once the wizard opens, click下一个。

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下一个屏幕询问硬件服务器是本地还是遥控器。如果将板连接到主机计算机，请选择本地计算机，如果连接到另一台计算机，请选择遥控器并填写主机名and港口字段。

点击下一个to continue.

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此屏幕提供了连接到硬件服务器的设备列表。如果只有一个连接，它将是显示的唯一设备。

点击下一个to continue.

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最终屏幕显示了向导中选择的选项的摘要。验证信息并单击Finish。这board is now connected to the hardware server.

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要用前面生成的位文件编程设备，请单击链接绿色横幅在窗户的顶部或单击按钮流导航器在下面。从打开的下拉列表中，选择设备进行编程（示例：：）和以下窗口将打开：

这Bitstream Filefield should be automatically filled in with the bit file generated earlier. If not, click thebutton at the right end of the field and navigate to
<项目目录>/<项目名称>。/ and select the bit file (Example:）。现在单击程序。This will connect to the board, clear the current configuration, and program it using the new bit file.

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At this point, the demo is now running on your board. Refer to theDescription本文档的一节有关它的作用更多信息。

Each analog input channel will control the brightness of anLEDas shown in the following table:

Changing Voltages by reconfiguring the circuit while the demo is running is fine. If you built the example circuit shown in the “Using the Latest Release” section, above, feel free to move jumpers around to test out the different nodes of the voltage divider.

所有与使用Zybo Z7有关的材料都可以在其上找到资源中心。

For a walkthrough of the process of creating a simple HDL project in Vivado, seeGetting Started with Vivado for Hardware-Only Designs。有关重要部分的信息GUI，以及在这里还可以找到修改，重建和运行此演示所需的步骤的间接讨论。

For technical support, please visit theFPGAsection of the Digilent Forum.