Basys 3 Keyboard Demo

The Keyboard Demo project demonstrates a simple usage of the Basys3's USB-HID and USB-UART ports. The behavior is as follows:

• The user presses a key on the keyboard, this sends a keyboard PS/2 scan code to the Basys3 over the USB-HID port. This scan code is read and transmitted to a terminal application via the USB-UART bridge. When the key is released, a scan code of F0XX is transmitted, indicating that the key with PS/2 code XX has been released.

• Basys 3 with a MicroUSB Programming Cable
• Vivado installation compatible with the latest release of this demo (2020.1)
  • SeeInstalling Vivado, Vitis, and Digilent Board Filesfor installation instructions.
• Serial Terminal application to receive messages printed by the demo
  • SeeInstalling and Using a Terminal Emulatorfor more information.
• USB Keyboard

First and foremost, releases - consisting of a set of files for download - are only compatible with a specific version of the Xilinx tools, as specified in the name of the release (referred to as arelease tag). In addition, releases are only compatible with the specified variant of the board. For example, a release tagged “20/DMA/2020.1” for the Zybo Z7 is only to be used with the -20 variant of the board and Vivado 2020.1.

The latest release version for this demo is highlighted in green.

Note:Releases for FPGA demos from before 2020.1 used a different git structure, and used a different release tag naming scheme.

Note for Advanced Users:All demos for the Basys 3 are provided through theBasys-3repository on Github. Further documentation on the structure of this repository can be found on this wiki'sDigilent FPGA Demo Git Repositoriespage.

Instructions on the use of the latest release can be found in this dropdown:

Using the Latest Release

Note:This workflow is common across many Digilent FPGA demos. Screenshots may not match the demo you are working with.

Important:These steps are only to be used with releases for Xilinx tools versions 2020.1 and newer. Older releases may require other flows, as noted in the table of releases.

First, download and extract the '*.xpr.zip' file from the demo release page, linked above.

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Open a Vivado Project from a Release

Launch Vivado

选择博士opdown corresponding to your operating system, below.

Windows

Open Vivado through the start menu or desktop shortcut created during the installation process.

Linux

Open a terminal, and change directory (cd) to a folder where log files for your Vivado session can be placed, then run the following commands:

source /Vivado//settings64.sh vivado

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In Vivado's welcome screen, use theOpen Projectbutton to navigate to and open the XPR file contained in the folder the release was extracted into.

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Build a Vivado Project

Note that if your project already has a generated bitstream, as indicated by the status in the top right corner of the window reading “write_bitstream Complete!”, then you can skip this section.

Generate a Bitstream

In order to create a file that can be used to program the target board, each stage of the “compilation pipeline” needs to be run.

This starts withSynthesis. Synthesis creates a description of the logic gates and connections between them required to perform the functionality described by the HDL files, given the constraints included in XDC files. To run Synthesis click eitherin the toolbar orin theFlow Navigator. The output of Synthesis is then passed to Implementation.

Implementationhas several steps. The steps that are always run areOpt Design(Optimize the design to fit on the target FPGA),Place Design(Lay out the design in the target FPGA fabric), andRoute Design(Route signals through the fabric). To run Implementation click eitherin the toolbar orin theFlow Navigator. This output is then passed on to the Bitstream Generator.

TheBitstream Generatorgenerates the final output file needed for programming the FPGA. To run Bitstream Generation click eitherin the toolbar orin theFlow Navigator. With no settings changed, the generator will create a '.bit' file.

Depending on the complexity of the design, the board used, and the strength of your computer, the process of building the project can take between 5 and 60 minutes. When complete, a pop up dialog will appear, prompting you to select one of several options. None are relevant for the purposes of this guide, so clickCancel. The “write_bitstream complete” status message can be seen in the top right corner of the window, indicating that the demo is ready to be deployed to your board.

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Set up the Basys 3

Plug the Basys 3 into the computer using the microUSB cable. Also plug the keyboard into the Basys 3.

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Program a Bitstream onto an FPGA Board

Vivado's Hardware Manager can be opened by clicking onOpen Hardware Managerat the bottom of the Flow Navigator pane on the left side of the Vivado window.

The first step to programming a device is to connect the Vivado Hardware Server to it as a target. To get to theOpen Hardware Targetwizard click thelink in the green banner near the top of the window. From the drop-down that opens, select.

Once the wizard opens, clickNext.

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The next screen asks if the hardware server is local or remote. If the board is connected to the host computer choose local, if it is connected to another machine choose remote and fill in theHost NameandPortfields.

ClickNextto continue.

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这个屏幕给设备连接到t的列表he hardware server. If there is only one connected it will be the only device shown.

ClickNextto continue.

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The final screen shows a summary of the options selected in the wizard. Verify the information and clickFinish. The board is now connected to the hardware server.

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To program the device with the bit file generated earlier, either click thelink in thegreen bannerat the top of the window or click thebutton in theFlow Navigatorunder. From the drop-down that opens, select the device to program (Example:) and the following window will open:

TheBitstream Filefield should be automatically filled in with the bit file generated earlier. If not, click thebutton at the right end of the field and navigate to
/.runs/impl_1/ and select the bit file (Example:). Now clickProgram. This will connect to the board, clear the current configuration, and program it using the new bit file.

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At this point, the demo is now running on your board. Refer to theDescriptionandFunctionalitysections of this document for more information on what it does.

When a button is pressed, the value of the scan code will be converted toASCIIand transmitted to the terminal. In the picture, 'a' is pressed, so a scan code of “1C” is sent to the terminal. The expected scan code for each key can be found in the keyboard diagram at the top of this guide.

When the 'a' key is released, a scan code of “F0 1C” is sent over UART.

When multiple keys are pressed their scan codes are sent over UART in order. In this case, Q (“15”) was pressed, followed by W (“1D”).

All materials related to the use of the Basys 3 can be found on itsResource Center.

For a walkthrough of the process of creating a simple HDL project in Vivado, seeGetting Started with Vivado for Hardware-Only Designs. Information on important parts of theGUI, and indirect discussion of the steps required to modify, rebuild, and run this demo in hardware can also be found here.

For technical support, please visit theFPGAsection of the Digilent Forum.