Genesys 2 - Getting Started with Microblaze Servers

笔记：The Genesys2 uses a Gigabit Ethernet module which requires the TEMAC IP that isVivado Webpack中未包含。为了完成本教程之后,您必须either purchase a license for the TEMAC IP or get the evaluation license for free from their website by following本指南。

This guide will provide a step by step walk-through of creating a Microblaze based hardware design using the Vivado IP Integrator that will build over theGetting Started with Microblaze通过使用Genesys2 FPGA板的机上以太网端口和GPIO进行指南。

在本教程的末尾，您将对Genesys2进行全面的硬件设计，该设计利用由Microblaze SoftCore处理器块管理的Genesys2上的各种硬件端口。

NOTE: The Genesys2 requires Vivado Design Edition or System Edition which supports the Kintex-7 FPGA. This is not the same as the free webpack version

Important:This guide only officially supports Vivado and Xilinx SDK 2015.4. Differences in IP and drivers between different versions of the tools make it so that while the steps presented here may be useful in other versions, unforeseen issues may arise. Proceed at your own risk.

• Digilent Genesys2 FPGA板
• 2个用于UART通信和JTAG编程的微电缆
• Ethernet Cable

• Xilinx Vivado 2015.X
  • System Edition or Design Edition must be installed to support the Kintex-7 FPGA
• Xilinx SDK
  • Same version as your Vivado installation
• Serial Terminal Application
  • Tera Term is used in this tutorial
• 安装了TEMAC IP许可证
  • 遵循此Wiki指南:安装TEMAC IP的120天评估许可证。

• Board Support Files– These files will describeGPIOinterfaces on your board and make it easier to select your FPGA board and addGPIOIP块。
  • 遵循此Wiki指南Vivado Board Files for Digilent 7-Series FPGA Boards关于如何安装Vivado 2015.x的董事会支持文件

When you first run Vivado this will be the main start window where you can create a new project or open a recent one.

1.1）单击Create New Project。Choose the Project Name and Location such that there are没有空白的空间。对于项目名称，文件名和位置路径，这是一个重要的命名约定。
Underscore in a good substitute for empty spaces.

最好有一个用于Vivado项目的专用文件夹，最好是最小的路径长度。示例：c：/vivado_projects。

Name your Project and select the Project location and clickNext。

1.2）选择项目类型为RTL Project。Leave the - do not specify sources box unchecked and clickNext。

1.3) We will not be importing or creating any files here, so clickNextuntil the part select screen.

1.4）如果您完成了Board Support File Wiki guide， 选择董事会。
Genesys2should be displayed in the selection list. A mismatch in selecting the correct board name will cause errors. Select theGenesys2and clickNext。

1.5) A summary of the new project design sources and target device is displayed. ClickFinish。

这是您可以创建基于IP的块设计或添加基于RTL的设计源的主要项目窗口。左侧的Flow Navigator面板提供了有关如何创建硬件设计，执行仿真，运行合成和实现并生成位文件的多个选项。您还可以使用硬件管理器直接从Vivado编程，并使用RTL项目的生成位文件编程。

为了设计，我们将使用IP集成器来创建新的块设计。

2.1）在左侧，您应该看到流导航器。选择Create Block Designunder the IP Integrator. Give a name to your design (without any empty spaces) and clickOk。



You have created a new block design.

3.1）单击Board标签（下面以橙色突出显示）



This list contains all of the components defined in the board file you installed before. These are already configured to work with several Vivado IPs.

3.2）单击并拖动DDR3 SDRAMcomponent onto the empty block design. Vivado will automatically connect the DDR3 SDRAM and system clock to the MIG IP.

3.3）单击Run Connection Automationin the green banner above. ClickOk。



Vivado will connect your system reset to sys_rst on the MIG.

4.1）单击 Add IPbutton and search forMicroblaze。



双击Microblaze将其添加到您的块设计中。

4.2）单击运行块自动化至open the Block automation for the Microblaze processor.

Here you can choose how much memory to give your Microblaze processor.配置选项至match the picture below, then clickOK。

4.3) Running the block automation will auto-generate a set of additional IP blocks which will be added to our hardware design automatically based on the options selected in the previous step.Do not click on Run Connection Automation yet.

5。1) Go into the董事会tab again and find theUSB UARTcomponent.单击并拖动this onto the block design to add the Uartlite block to your design.

5.2）找到Ethernet PHYanddrag this onto the block design至add the Ethernet block to your design.

5。3) Click the Add IPbutton and search forTimer。双击AXI Timer将其添加到您的块设计中。

5。4) Click运行块自动化在绿色的横幅中。然后单击OK在弹出的屏幕上。



This will create a new Ethernet DMA IP block as well as a clock wizard.

5.5）找到时钟向导axi_ethernet_0_refclk并连接CLK_IN1至这ui_clkoutput on themig_7series_0堵塞。

5。6) ClickRun Connection Automation在绿色的横幅中。Check the所有自动化checkbox and clickOK。



您可能会警告过时的自动化。只是Run Connection Automation再次在所有自动化上。这将为DDR存储器创建一个AXI互连，另一个用于外围组件。

6.1）找到Concat阻止并双击它以打开其设置。

6.2）更改Number of Ports至5。点击OK。

6.3）Concat Block取中断输入，并将其发送到微衬里控制器。



路由以下连接到输入Concatblock; order does not matter:
-interrupton theAXI Timer堵塞。
-mm2s_introutands2mm_introuton theaxi_ethernet_0_dma堵塞。
-MAC_IRQandinterrupton theaxi_ethernet_0堵塞。

7.1) Click the Regenerate Layoutbutton to rearrange your block design.

7.2) Select 验证设计。这将检查设计和连接错误。

7.3) After the design validation step we will proceed with creating a HDL System Wrapper. Click on theSources标签并找到您的块设计。

7.4) Right click on your block design and clickCreate HDL Wrapper。让Vivado管理包装纸和自动更新and clickOK。



这将在VHDL中创建一个顶部模块，并允许您生成一个Bitstream。

8.1) In the top toolbar in Vivado, click Generate Bitstream。这也可以在流导航器左下方的面板程序and Debug。
如果您尚未保存设计，则将获得提示来保存块设计。

8.2) The bit file generation will begin. The tool will runSynthesisandImplementation。After both synthesis and implementation have been successfully completed, the bit file will be created. You will find a status bar of Synthesis and Implementation running on the top right corner of the project window.

This process can take anywhere from5至60 minutesdepending on your computer.

8.3) After the bitstream has been generated, a message prompt will pop-up on the screen. You don't have to open the Implemented Design for this demo. Just clickCancel。

9.1) On the main toolbar, clickFile并选择Export Hardware。Check the box to包括Bitstreamand clickOK。这将为软件开发工具-Vivado SDK的系统包装器导出硬件设计。



A new file directory will be created underecho_server。SDKsimilar to the Vivado hardware design project name. Two other files,。sysdefand。hdf也是创建的。此步骤本质上创建了一个新的SDK工作区。

9.2）在主工具栏上，单击Fileand thenLaunch SDK。Leave both of the dropdown menus as their defaultLocal to Projectand clickOK。这将打开Xilinx SDK并导入您的硬件。

10.1) The HW design specification and included IP blocks are displayed in thesystem.hdffile. Xilinx SDK is independent of Vivado, i.e. from this point, you can create your SW project in C/C++ on top of the exported HW design. If necessary, you can also launch SDK directly from the SDK folder created in the main Vivado Project directory.

从这一点开始，如果您需要返回Vivado并对HW设计进行更改，则建议关闭SDK窗口并在Vivado进行所需的HW设计编辑。此后，您必须遵循创建新的HDL包装器的顺序，保存设计和BIT文件生成。然后必须将此新的位文件和系统包装器导出到SDK。

10.2）在Project Explorertab on the left, you can see your hardware platform.

system是您在Vivado创建的块设计的名称。该硬件平台具有所有HW设计定义，已添加的IP接口，外部输出信号信息和本地内存地址信息。

11.1) Click the New下拉箭头并选择Application Project。



Give your project a name that has no empty spaces and clickNext。

11.2）选择lwIP Echo Serverfrom the list of templates and clickOK。

You will see two new folders in theProject Explorer控制板。

• echo_server它包含所有的二进制文件,. c和. h(头吗) files
• echo_server_bsp这是董事会支持文件夹

echo_serveris our main working source folder. This also contains an important file shown here which is the “lscript.ld”. This is a Xilinx auto generated linker script file. Double click on this file to open.

11.3) Back in theProject Explorer，双击并打开system.mssunder theecho_server_bsp文件夹。点击Modify this BSP's Settings。

11.4) Clicklwip141这n findtemac_adapter_optionsand click the arrow. Findphy_link_speedand change the Value toCONFIG_LINKSPEED100。If your router supports Gigabit transfers, change this value toCONFIG_LINKSPEED1000。点击OK。

12.1）确保Genesys2通过两个打开并连接到主机PCJTAGUSB portand这UARTUSB port.

On the top toolbar, click the 程序FPGA按钮。

12.2) Click程序至program your FPGA with your hardware design.

13.1) Open up a Serial Terminal application (Tera Term). Connect to the Genesys2 UART port with a baud rate of 9600. This baud rate can be altered in your block design by double clicking the Uartlite block.

14.1）确保在开始之前将Genesys2插入路由器中。

14.2) Back in SDK, select yourecho_serverproject and click the Run As…按钮。选择在硬件（系统调试器）上启动and clickOK。

14.3) Your program will run and you should see the IP information inside of your Serial Terminal.

14.4) Connect to the echo server by opening another terminal and connecting to the端口7上的IP。

14.5) Test your echo server by typing something into the terminal. Depending on your settings, you might not see the characters until you pressEnter。当您这样做时，该消息将发送到Echo服务器，并将回声回到您的终端！