Using a Peripheral with a Hierarchical Block in Vivado IPI and Vitis

In Vivado, a分层块is a block design within a block design. These blocks allow engineers to partition their designs into separate functional groups. This guide steps through the process of adding a pre-existing hierarchical block to a block design, recreating its example software application, and running the design in hardware.

笔记：Screenshots presented in this guide may not have been taken with your version of the tools. The workflow presented here has been verified in Vivado 2020.1. While there are some differences between 2020.1 and older versions of the tools, older screenshots have been checked, and contain the same user interfaces that are seen in 2020.1.

• A Digilent FPGA development board.
• 安装了带有Vivado的计算机。
  • See the安装Vivado，Vitis和Digilent板文件指南以获取更多信息。
• Familiarity with Vivado IP Integrator and a base block design to work from.
  • Following theBaremetal软件项目的Vivado和Vitis入门指南将导致适合所有要求的设计。

A ZIP archive including all required IP, software examples, and hierarchy scripts for each peripheral this guide supports can be downloaded from Github here:vivado-library-hierarchies.zip。

Download this file, and extract it to somewhere memorable on your computer.

一些用户可能希望通过git访问这些文件，这提供了一种方法，可以将以后提取任何更新或修复程序。以下下拉列表中详细介绍了将这些来源克隆的来源。

Getting Sources through Git

笔记：In order to use git commands,git必须安装在计算机上。有各种不同的应用程序可用于与GIT工具进行交互。下面的代码块详细说明了bash shell中使用的命令。

Check if vivado-library is already included in the Vivado project, if it is not, then it should be cloned:

cd (somewhere memorable) git clone https://github.com/digilent/vivado-library -b hierarchies

否则（如果项目中已经包含了vivado-library的单独克隆），请使用git工具检查分支：

Warning!如果来自库中的IP已经包含在项目中，则检查其他分支可能会导致其更改。当心！

cd (path)/vivado-library git checkout hierarchies

source (path)/vivado-library/hierarchies/(hierarchy of choice)/create_hier.tcl

这next step, constraining the Hierarchy's external port/s, has two different Workflows:

1. If a board was selected when creating the project, theBoard Flowcan be used for this step.
2. 如果被选中,而不是一部分,或Board Flow cannot be used for whatever reason, theManual Constraint Flowshould be used instead.

打开dropdown for the chosen Workflow, below, and follow the instructions.

笔记：This step is only required for Pmod hierarchical blocks. Zmod hierarchical scripts automatically create their external ports. For the purposes of this guide, consider the Zmod's external ports to have been created using the Manual Constraint Flow.

Board Flow

Go to Vivado'sBoard选项卡并选择一个PMOD连接器以连接到层次结构块。右键单击连接器的条目，通常命名为“连接器JA”，然后选择Connect Board Component。In the popup window, underConnect to existing IP, select the “Pmod_out” interface of the Hierarchy's Pmod Bridge IP. ClickOK。

Manual Constraint Flow

选择PMOD_OUT端口，然后右键单击并选择Make External。选择the newly created external interface port (named something like “Pmod_out_0”) in the design, and give it a memorable name.

This step works a little differently depending on whether the peripheral targeted by the hierarchical block is aZMODor aPmod。选择the dropdown for the chosen peripheral:

Pmod

If theBoard Flowwas chosen, open the README.txt file in the hierarchical block's folder in vivado-library-hierarchies to determine whether any additional constraints are required. If there are none,skip the rest of this section。

When the Hierarchy was created, a constraint file, named “(Hierarchy Name)_Pmod_out.xdc”, was imported into the Vivado project. This file contains a template for all required constraints, regardless of the flow used. Open it now from theSourcespane, by finding it underConstraints并双击它。

限制Board Flow默认情况下没有注销。

If theManual Constraint Flow被选中，通过在每条线的开头删除“＃”符号，从“ set_property”开始的任何评论的线条。

这text “FIXME” is used in the constraint file to indicate places where values specific to the board and design must be manually entered.

Two types of manually entered values are typical of constraint files in these Hierarchies:

Port Names:
这些fixme后文本“get_ports”。这correct values for these FIXMEs can be found by reviewing the HDL wrapper file created in the previous step. Find the names of the ports of the Pmod_out interface that is connected to the hierarchy within the port map of the HDL wrapper. Enter these names into the corresponding places in the hierarchy's constraints file.

位置约束：
这se FIXMEs come after the text “PACKAGE_PIN”, and are only required in theManual Constraint Flow。这correct values for these FIXMEs can be found by reviewing the master XDC file for the target board. Master XDC files for Digilent boards can be found in theDigilent-XDCrepository on Github. Find the LOC property values that correspond to the Pmod connector that the hierarchical block's Pmod_out port is to be connected to. Enter these values into the corresponding places in the hierarchy's constraint file.

ZMOD

当Create_hier.tcl用于ZMOD层次结构块时，导入了约束文件，其中包含脚本创建的每个外部端口的模板约束。约束文件以脚本创建的层次结构块命名，其次是特定ZMOD的名称，例如：“ Zmodadc_0_zmodadc.xdc”。约束文件可以在Vivado IP Integrato源窗格的“约束部分”下找到。

At time of writing, each Zmod Hierarchical Block provides template constraints for each of the Eclypse Z7's Zmod Ports. By default, the ZmodADCis connected to the Eclypse Z7's Zmod Port A, and the ZmodDACis connected to Zmod Port B. To connect to a different port, the user need only comment out the section of the xdc corresponding to the default port, and uncomment the section corresponding to the chosen port.

对于其他董事会，用户必须用所选板的主XDC文件中的相应位置替换ZMOD端口的Package_pin位置约束，可以通过该文件获得Digilent-XDCrepository on GitHub.

This section covers creating a baremetal software application from example source files in Vitis.

Export Hardware

建立项目后，必须将设计从Vivado出口，以便Vitis可以访问有关正在开发软件应用程序的硬件的信息。这包括连接到处理器，其驱动程序，地址等的IP集。生成Bitstream后出口硬件可以使您可以直接从Vitis内部编程板。

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To export the hardware design, click导出→导出硬件in theFile菜单。

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这wizard that pops up guides you through the options available for hardware export. The first screen allows you to select aFixedor可扩展platform. In this case, choose a Fixed platform and clickNextto continue.

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这输出screen allows you to select whether only the hardware specification (Pre-synthesis）应出口，或者是否应包括在内。由于已经生成了Bitstream，因此应将其包含在平台中，以便Vitis可以自动找出编程板时的位置。选择Include bitstreamand clickNextto continue.

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这文件屏幕给你为t选项选择一个名称he Xilinx Shell Architecture (XSA) file, and provide a path to a folder that the file will be placed within. Give your XSA file a name, and choose a memorable location to place it in. This file will later be imported into Vitis, so take a note of where it is placed and what it is called.

Important:Do not use spaces in the file name or export path. Underscores or骆驼香烟盒are recommended instead.

ClickNextto continue.

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这final screen of the wizard summarizes the options you selected. ClickFinish。

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Launch Vitis

在下面选择与您的操作系统相对应的下拉菜单。

Windows

打开Vitis through the start menu or desktop shortcut created during the installation process.

Linux

打开a terminal and run the following commands. The install path is /opt/Xilinx by default.

source /Vitis/2020.1/settings64.sh vitis

笔记：不管OS, if Vivado is open, Vitis can also be launched through theTools → Launch Vitistoolbar option.

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Upon launching Vitis, a dialog will appear where a workspace must be chosen. The workspace is the directory where all of the projects and files for the application being developed will live. If a folder that does not currently exist is chosen, it will be created. Choose a workspace and clickLaunchto finish launching Vitis.

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创建一个空应用程序

With Vitis open, an application project must be created to hold your source files. In creating an application project, a hardware platform will also be created from an XSA file previously exported from Vivado.

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On Vitis' welcome screen, clickCreate Application Project。这wizard that launches will be used to create and configure a new application.

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这first screen of the wizard is a welcome page, which summarizes what each of the components of a software design are. ClickNextto continue.

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接下来，必须创建应用程序目标的平台。打开Create a new platform…tab.

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Browseyour file system to find the Xilinx Shell Architecture previously exported from Vivado. With the XSA file highlighted, click打开选择它并返回Platformscreen of the wizard.

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Once you have found the XSA file and opened it, make sure that it is selected in theHardware Specification列表。给您的平台一个名称（默认情况下使用XSA文件的名称，并且可以正常工作）。这Generate boot componentsbox can be used to automatically build all of the additional components necessary to boot the application from flash memory or an SD card. Leaving this box checked is recommended. ClickNextto continue.

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这next screen is used to set some options for the application project and the system project. The names of both projects can be set, as well as which processor core will be used to run the application. All settings can be left as defaults. ClickNextto continue.

笔记：A system project can contain multiple application projects, which can all be run at once.

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Next, the domain that the application project operates in will be defined. In this case all default settings will be used. ClickNextto continue.

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Lastly, a template project will be chosen. Each template pre-configures the application project for a different purpose. Depending on the whether your application will be written in C or C++, chooseEmpty Applicationor空应用程序（C ++）。You will be adding an example main source file later, as opposed to working from and editing an example.

ClickFinishto finish creating the project.

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将示例资源添加到应用程序

Copy all of the files from the selected hierarchical block'ssdk_sourcesfolder (in the vivado-library-hierarchies folder), then paste them into the application project'ssrcfolder.

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Launch the Application

Launch a Vitis Baremetal Software Application

First, many applications require that a serial console is connected to the board, so that standard output (from print statements) can be viewed. For this purpose, a serial terminal should be used. Use a serial terminal application to connect to the board's serial port. Unless otherwise stated, Zynq designs use a baud rate of 115200 and Microblaze designs with an AXI UART Lite IP use a baud rate of 9600.

笔记：While Vitis has a built in serial terminal included in its Debug view, it sends characters to a board on a line-by-line basis. Some software examples require the use of character-by-character reception of data.tera术语orPuTTYare recommended if you are not sure what will work.

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In theExplorer屏幕左侧的窗格，右键单击要运行的应用程序或系统项目，然后选择Run as → 1 Launch on Hardware (Single Application Debug)。FPGA将使用Bitstream编程，软件构建创建的ELF文件已加载到系统内存中，并且应用程序项目将开始运行。您将需要点击回到Vitis Serial Terminalfrom theConsoletab.

笔记：一旦项目至少运行一次，您可以使用绿色运行按钮（) in the toolbar at the top of the screen to program the board instead.

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Now that the hierarchical block's example design is running, modifications can easily be made to the hardware or software.

这Vitis sources provided with the hierarchical blocks are set up such that they can be easily included in any design using that block. The subfolder below sdk_sources contains all necessary drivers for the block.

For more reference materials and guides on the Digilent products being used, navigate to their resource centers, which can be found through this wiki's可编程逻辑page.

For technical support, please visit the数字Forums。