Nexys A7 XADC Demo

This project is a Vivado demo using the Nexys A7-100T's analog-to-digital converter circuitry, switches, LEDs, and seven-segment display, written in Verilog. When programmed onto the board, voltage levels between 0 and 1 Volt are read off of the JXADC header. The 16 User LEDs increment from right to left as the voltage difference between the selected channel's pins gets larger. The seven-segment display shows the voltage difference between the selected channel's pins in volts. SW0 and SW1 select which XADC channel is displayed.

See the Nexys A7'sReference Manualfor more information about how the Artix 7 FPGA's XADC is connected to header JXADC.

• Nexys A7 with a MicroUSB Programming Cable
• Vivado installation compatible with the latest release of this demo (2020.1)
  • SeeInstalling Vivado, Vitis, and Digilent Board Filesfor installation instructions.
• Wires, Breadboard and a Circuit to Test

The following releases of this demo can be used with instructions found in the corresponding READMEs in order to run the demo.

Releases are only compatible with the version of the Xilinx tools specified in the release version number. In addition, releases are only compatible with the specified variant of the board. For example, the v2020.1-1 release for Nexys A7-100T can only be used with Vivado 2020.1 and Nexys A7-100T variant of the board.

Note:最新的是lease tags for each variant and branch are highlighted in green.

Note for Advanced Users:All demos for the Nexys A7 are provided through theNexys-A7repository on Github. Further documentation on the structure of this repository can be found on this wiki'sDigilent FPGA Demo Git Repositoriespage.

Instructions on the use of the latest release can be found in this dropdown:

Using the Latest Release

Note:This workflow is common across many Digilent FPGA demos. Screenshots may not match the demo you are working with.

Important:These steps are only to be used with releases for Xilinx tools versions 2020.1 and newer. Older releases may require other flows, as noted in the table of releases.

First, download and extract the '*.xpr.zip' file from the demo release page, linked above.

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Open a Vivado Project from a Release

Launch Vivado

Select the dropdown corresponding to your operating system, below.

Windows

Open Vivado through the start menu or desktop shortcut created during the installation process.

Linux

Open a terminal, and change directory (cd) to a folder where log files for your Vivado session can be placed, then run the following commands:

source /Vivado//settings64.sh vivado

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In Vivado's welcome screen, use theOpen Projectbutton to navigate to and open the XPR file contained in the folder the release was extracted into.

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Build a Vivado Project

Note that if your project already has a generated bitstream, as indicated by the status in the top right corner of the window reading “write_bitstream Complete!”, then you can skip this section.

Generate a Bitstream

In order to create a file that can be used to program the target board, each stage of the “compilation pipeline” needs to be run.

This starts withSynthesis. Synthesis creates a description of the logic gates and connections between them required to perform the functionality described by the HDL files, given the constraints included in XDC files. To run Synthesis click eitherin the toolbar orin theFlow Navigator. The output of Synthesis is then passed to Implementation.

Implementationhas several steps. The steps that are always run areOpt Design(Optimize the design to fit on the target FPGA),Place Design(Lay out the design in the target FPGA fabric), andRoute Design(Route signals through the fabric). To run Implementation click eitherin the toolbar orin theFlow Navigator. This output is then passed on to the Bitstream Generator.

TheBitstream Generatorgenerates the final output file needed for programming the FPGA. To run Bitstream Generation click eitherin the toolbar orin theFlow Navigator. With no settings changed, the generator will create a '.bit' file.

Depending on the complexity of the design, the board used, and the strength of your computer, the process of building the project can take between 5 and 60 minutes. When complete, a pop up dialog will appear, prompting you to select one of several options. None are relevant for the purposes of this guide, so clickCancel. The “write_bitstream complete” status message can be seen in the top right corner of the window, indicating that the demo is ready to be deployed to your board.

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Set up the Nexys A7

Plug the Nexys A7 into the computer using the microUSB cable. The circuit and wires can be attached after the demo is already running.

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Program a Bitstream onto an FPGA Board

Vivado's Hardware Manager can be opened by clicking onOpen Hardware Managerat the bottom of the Flow Navigator pane on the left side of the Vivado window.

The first step to programming a device is to connect the Vivado Hardware Server to it as a target. To get to theOpen Hardware Targetwizard click thelink in the green banner near the top of the window. From the drop-down that opens, select.

Once the wizard opens, clickNext.

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The next screen asks if the hardware server is local or remote. If the board is connected to the host computer choose local, if it is connected to another machine choose remote and fill in theHost NameandPortfields.

ClickNextto continue.

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This screen gives a list of devices connected to the hardware server. If there is only one connected it will be the only device shown.

ClickNextto continue.

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The final screen shows a summary of the options selected in the wizard. Verify the information and clickFinish. The board is now connected to the hardware server.

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To program the device with the bit file generated earlier, either click thelink in thegreen bannerat the top of the window or click thebutton in theFlow Navigatorunder. From the drop-down that opens, select the device to program (Example:) and the following window will open:

TheBitstream Filefield should be automatically filled in with the bit file generated earlier. If not, click thebutton at the right end of the field and navigate to
<项目目录> / <项目名称>。runs/impl_1/ and select the bit file (Example:). Now clickProgram. This will connect to the board, clear the current configuration, and program it using the new bit file.

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At this point, the demo is now running on your board. Refer to theDescriptionandFunctionalitysections of this document for more information on what it does.

The demo reads analog data from each enabled XADC channel (set using sw0 and sw1). The 7-Segment display shows the current voltage across the selected xadc pins. The LEDs turn on from right to left as the input voltage increases. The switch selections for each channel can be seen in the table below:

All materials related to the use of the Nexys A7 can be found on itsResource Center.

For a walkthrough of the process of creating a simple HDL project in Vivado, seeGetting Started with Vivado for Hardware-Only Designs. Information on important parts of theGUI, and indirect discussion of the steps required to modify, rebuild, and run this demo in hardware can also be found there.

For technical support, please visit theFPGAsection of the Digilent Forum.