Arty - Getting Started with Microblaze

This guide will provide a step by step walk-through of creating a Microblaze based hardware design using the Vivado IP Integrator for the Arty FPGA board.

At the end of this tutorial you will have:

• Created a Microblaze based hardware ( HW ) design in Xilinx Vivado

• Created .C Project in Xilinx Vivado SDK ( Software Development Kit) to display Hello World through hardware design.

• 最终的输出显示在SDK控制台and Tera Term

Microblaze is a soft IP core from Xilinx that will implement a microprocessor entirely within the Xilinx FPGA general purpose memory and logic fabric. For this tutorial, we are going to add a Microblaze IP block using the Vivado IP Integrator tool.

In addition to the Microblaze IP block, we would also like to make use of the DDR3 SDRAM component on the Arty. Therefore a MIG ( Memory Interface Generator ) IP block will be added to our design.

Finally, a UART ( universal asynchronous receiver/transmitter ) IP block will be added to communicate between the host PC and the soft processor core running on the Arty.

I. Vivado

• Open Vivado and select Arty board
• Create an new Vivado Project
• Create empty block design workspace inside the new project
• Add required IP blocks using the IP integrator tool and build Hardware Design
• Validate and save block design
• Create HDL system wrapper
• Run design Synthesis and Implementation
• Generate Bit File
• Export Hardware Design including the generated bit stream file to SDK tool
• Launch SDK

Now the Hardware design is exported to the SDK tool. The Vivado to SDK hand-off is done internally through Vivado. We will use SDK to create a Software application that will use the customized board interface data and FPGA hardware configuration by importing the hardware design information from Vivado.

II. SDK

• Create new application project and select default Hello World template
• Program FPGA
• Run configuration by selecting the correct UART COM Port and Baud Rate

• Familiarity with Vivado
• Block Design Experience

• Digilent Arty FPGA Board
• Micro USB Cable
  • Used for UART communication, JTAG programming, and Power

• Xilinx Vivado 2015.4 with the SDK package.
  • Newer versions of Vivado may also work
• Digilent Board Support Files
  • Follow thewiki guideon how to install Board Support Files for Vivado 2015.X

1.1) Open up Vivado and clickCreate New Projectto open Vivado's New Project wizard.

1.2) A new window will open up, clickNext你会看到下面的屏幕。命名项目(no spaces!) and choose your project saving directory before clickingNext. Underscores are a good substitute for empty spaces.

1.3) We will be building this project from the ground up and adding our own sources so we will want to create an RTL project. Select RTL Project and make sure theDo not specify sources at this timebox is checked. ClickNext.

1.4) If you have followed the Board Support File Wiki guide then selectBoards. The filter options can be used to quickly find the Arty board, by selecting “digilentinc.com” for Vendor, and “Arty” for Display Name.Artyshould be displayed in the selection list. Selecting a different board name will cause errors later. ClickNext.

1.5) A summary of the new project design sources and target device is displayed. ClickFinish.

At this point you have successfully created a project that will properly communicate with the Arty.

This is the main project window where you can create a IP based block design or add RTL based design sources. The flow navigator panel on the left provides multiple options on how to create a hardware design, perform simulation, run synthesis and implementation and generate a bit file. You can also program the board directly from Vivado with the generated bit file for an RTL project using the Hardware Manager.

For our design, we will use the IP Integrator to create a new block design.

2.1) On the left you should see the Flow Navigator. SelectCreate Block Designunder the IP Integrator. Give a name to your design (without any empty spaces) and clickOK.



You have created a new block design.

3.1) Click theBoardtab (Highlighted in orange below)



This list contains all of the components defined in the board file you installed before. These are already configured to work with several Vivado IPs.

3.2) Click and drag theSystem Clockcomponent onto the empty block design. Vivado will automatically connect this system clock to a new Clocking Wizard block.

3.3) Double click theClocking Wizardblock to customize it. Click on theOutput Clockstab and changeclk_out1to “166.667”MHz. Enableclk_out2and set it to “200.0”MHz. Set theReset TypetoActive Low



ClickOKto close this window.

3.4) Click and drag theDDR3 SDRAMcomponent onto the empty block design. Vivado will automatically connect the DDR3 SDRAM and some dummy clock ports to the MIG IP.

3.5)删除theclk_ref_iandsys_clk_iports by clicking them and pressing the删除key, or by right clicking them and selecting删除.

3.6) Connectclk_out1tosys_clk_ion the MIG block. Connectclk_out2toclk_ref_i.

3.7) ClickRun Connection Automationin the green banner above. The default settings are fine, so clickOK.



Vivado will connect your system reset to sys_rst on the MIG.Connectthis new reset port to theresetninput on the Clock Wizard block.

4.1) Click the Add IPbutton and search forMicroblaze.



Double clickMicroblazeto add it to your block design.

4.2) ClickRun Block Automationto open the Block automation for the Microblaze processor.

Here you can choose how much memory to give your Microblaze processor.Configure the optionsto match the picture below, then clickOK. Make sure that you set the Clock Connection to/mig_7series_0/ui_clk.

4.3) Running the block automation will auto-generate a set of additional IP blocks which will be added to our hardware design automatically based on the options selected in the previous step.Do Notclick onRun Connection Automationyet.

5.1) Go into theBoardstab again and find theUSB UARTcomponent.Click and dragthis onto the block design to add the Uartlite block to your design.

5.2) ClickRun Connection Automationin the green banner. Check theAll Automationcheckbox and clickOK.



This will create one AXI Interconnect for the DDR Memory and another for peripheral components.
Click the Regenerate Layoutbutton to rearrange your block design.

6.1) Select Validate Design. This will check for design and connection errors.

6.2) After the design validation step we will proceed with creating a HDL System Wrapper. Click on theSourcestab and find your block design.



Right click on your block design and clickCreate HDL Wrapper. Make sureLet Vivado manage wrapper and auto-updateis selected and clickOK.



This will create a top module in Verilog and will allow you to generate a bitstream.

7.1) In the top toolbar in Vivado, click Generate Bitstream. This can also be found in theFlow Navigatorpanel on the left, underProgram and Debug.
If you haven't already saved your design, you will get a prompt to save the block design.

7.2) The bit file generation will begin. The tool will runSynthesisandImplementation. After both synthesis and implementation have been successfully completed, the bit file will be created. You will find a status bar of Synthesis and Implementation running on the top right corner of the project window.

This process can take anywhere from2 to 20 minutesdepending on your computer.

7.3) After the bitstream has been generated, a message prompt will pop-up on the screen. You don't have to open the Implemented Design for this demo. Just clickCancel.

8.1) On the main toolbar, clickFileand selectExport→Export Hardware. Check the box toInclude Bitstreamand clickOK. This will export the hardware design with system wrapper for the Software Development Tool - Vivado SDK.



A new file directory will be created underHello_World.SDKsimilar to the Vivado hardware design project name. Two other files,.sysdefand.hdf也创造了。这一步基本上creates a new SDK Workspace.

8.2) On the main toolbar, clickFileand thenLaunch SDK. Leave both of the dropdown menus as their defaultLocal to Projectand clickOK. This will open Xilinx SDK and import your hardware.

9.1) The HW design specification and included IP blocks are displayed in thesystem.hdffile. Xilinx SDK is independent of Vivado, i.e. from this point, you can create your SW project in C/C++ on top of the exported HW design. If necessary, you can also launch SDK directly from the SDK folder created in the main Vivado Project directory.

From this point, if you need to go back to Vivado and make changes to the HW design, then it is recommended to close the SDK window and make the required HW design edits in Vivado. After this you must follow the sequence of creating a new HDL wrapper, save design and bit file generation. This new bit file and system wrapper must then be exported to SDK.

9.2) Within theProject Explorertab on the left, you can see your hardware platform.

systemis the name of your block design created in Vivado. This hardware platform has all the HW design definitions, IP interfaces that have been added, external output signal information and local memory address information.

10.1) Click the Newdropdown arrow and selectXilinx→Application Project.



Give your project a name that has no empty spaces and clickNext.

10.2) SelectHello Worldfrom the list of templates and clickFinish.

You will see two new folders in theProject Explorerpanel.

• Hello_worldwhich contains all the binaries, .C and .H (Header) files
• Hello_world_bspwhich is the board support folder

Hello_worldis our main working source folder. This also contains an important file shown here which is the “lscript.ld”. This is a Xilinx auto generated linker script file. Double click on this file to open.

10.3) Back in theProject Explorer, double click and openhelloworld.cunder thesrcfolder.

This is the main .C file which will print “Hello World” in the console when executed.

11.1) Make sure that the Arty is turned on and connected to the host PC via the USB-JTAG port - this port will serve dual purpose as the USB-UART connection to the Microblaze.

On the top toolbar, click the Program FPGAbutton.

11.2) ClickProgramto program your FPGA with your hardware design.

12.1) Open up a Serial Terminal application (Tera Term). Connect to the Arty UART port with a baud rate of 9600. This baud rate can be altered in your block design by double clicking the Uartlite block.

13.1) Back in SDK, select yourHello_worldproject and click the Run As…button. SelectLaunch on Hardware (System Debugger)and clickOK.

13.2) Your program will run and you should see “Hello World” pop up inside of your Serial Terminal. Hooray!