Basys 3 Getting started in Microblaze

本指南将为Basys 3 FPGA板上使用Vivado IP集成器创建基于微蓝光的硬件设计的逐步演练。

At the end of this tutorial you will have:

• Created a Microblaze based hardware ( HW ) design in Xilinx Vivado

• Created a .C Project in Xilinx Vivado SDK ( Software Development Kit) to display Hello World using the hardware design shown in the previous step

• Displayed the final output on both the SDK console and Tera Term

• Digilent Basys 3 FPGA板和Micro USB电缆用于UART通信和JTAG编程

• Xilinx Vivado 2016.X带有SDK包。

• Board Support Files
  • These files will describeGPIO在terfaces on your board and make it easier to select your FPGA board and addGPIOIP块
  • 遵循本Wiki指南（Vivado Board Files for Digilent 7-Series FPGA Boards) on how to install Board Support Files for Vivado

- -

Microblaze是Xilinx的软IP核心，它将完全在Xilinx FPGA通用记忆和逻辑结构中实现微处理器。对于本教程，我们将使用Vivado IP集成器工具添加一个微封闭式IP块。

In addition to the Microblaze IP block, a UART ( universal asynchronous receiver/transmitter ) IP block will be added to communicate between the host PC and the soft processor core running on the Basys 3.

I. Vivado

• 打开Vivado并选择Basys 3板
• Create an new Vivado Project
• Create empty block design workspace inside the new project
• Add required IP blocks using the IP integrator tool and build Hardware Design
• 验证并保存块设计
• 创建HDL系统包装器
• Run design Synthesis and Implementation
• Generate Bit File
• 导出硬件设计，包括生成的位流文件到SDK工具
• Launch SDK

现在，硬件设计导出到SDK工具。Vivado到SDK交接是通过Vivado内部完成的。我们将使用SDK创建一个软件应用程序，该应用程序将通过从Vivado导入硬件设计信息来使用自定义的板接口数据和FPGA硬件配置。

ii。SDK

• 创建新的应用程序项目并选择默认Hello World模板
• 程序FPGA
• 通过选择正确的UART COM端口和波特率来运行配置

When you first run Vivado this will be the main start window where you can create a new project or open a recent one.

1.1）单击Create New Project。Choose the Project Name and Location such that there are没有空白的空间。This is an important naming convention to follow for project names, file names and location paths. Underscore is a good substitute for empty spaces. It is good practice to have a dedicated folder for Vivado Projects, preferably with the smallest possible path length. Example: C:/Vivado_Projects. Name your Project and select the Project location and clickNext。

1.2）选择项目类型为RTL Project。Leave theDo not specify sourcesbox unchecked and clickNext。

1.3) If you have followed the Board Support File Wiki guide then click next until you can select董事会。从过滤器选项中，对供应商，显示名称和董事会修订版进行了必要的选择。Basys 3should be displayed in the selection list. A mismatch in selecting the correct board name will cause errors. Choose Basys 3 and click next.

1.4) A summary of the new project design sources and target device is displayed. ClickFinish。

2.1）这是您可以创建基于IP的块设计或添加基于RTL的设计源的主要项目窗口。左侧的Flow Navigator面板提供了有关如何创建硬件设计，执行仿真，运行合成和实现并生成位文件的多个选项。您还可以使用硬件管理器直接从Vivado编程，并使用RTL项目的生成位文件编程。为了设计，我们将使用IP集成器来创建新的块设计。

2.2）在左侧，您应该看到流导航器。选择Create Block Designunder the IP Integrator. Give a name to your design without any empty spaces.

2.3) An empty design workspace is created where you can add IP blocks. Add an IP core by clicking on the Add IPicon. This should open a catalog of pre-built IP blocks from Xilinx IP repository.

3.1）单击Boardtab

This list contains all of the components defined in the board file you installed before. These are already configured to work with several Vivado IPs.

3.2）单击并拖动System Clock组件到空块设计。Vivado将自动将此系统时钟连接到新的时钟向导块。

3.3) Double click theClocking Wizardblock to customize it. Click on the输出时钟tab. Make sureclk_out1是“ 100.000”和Reset TypeisActive High

4.1）通过单击 Add IPicon. Search for “Microblaze” and double click on it to add the IP block to your design. This is the Xilinx Microblaze IP block. When a new IP block is added the user can customize the block properties by either clicking on the运行块自动化消息提示或双击块本身。

4.2) Select运行块自动化and a customization assistant window will open with default settings.

4.3）更改块选项中的默认设置，如下所示，然后单击OK。这将使用我们的新用户设置自定义块。

Local Memory: 128KB
Local Memory ECC: None
Cache Configuration: None
调试模块：仅调试
Peripheral AXI Port: Enabled
Interrupt Controller: unchecked
Clock Connection: /clk_wiz0/clk_out1(100 MHZ)



4.4) Running the block automation will auto-generate a set of additional IP blocks which will be added to our hardware design automatically based on the options selected in the previous step.Do not click on Run Connection Automation yet.

5.1）进入董事会tab again and find theUSB UARTcomponent.单击并拖动this onto the block design to add the Uartlite block to your design.

：

5.2) ClickRun Connection Automation在绿色的横幅中。检查所有自动化框，然后单击OK。

5.3）单击Run Connection Automation再次在绿色横幅中。检查所有自动化框，然后单击OK。

5.4) Select 验证设计。这将检查设计和连接错误。


5.5）单击 Regenerate Layoutbutton to rearrange your block design. The block design should look like



5.6）选择 验证设计。这将检查设计和连接错误。

6.1）在设计验证步骤之后，我们将继续创建HDL系统包装器。单击Sources标签并找到您的块设计。



6.2)右键单击你块设计和点击Create HDL Wrapper。确保让Vivado管理包装纸和自动更新is selected and clickOK。



这将在Verilog中创建一个顶部模块，并允许您生成一个botstream。

7.1) Click Generate bitstream

8.1）在主工具栏上，单击File并选择导出→导出硬件。检查box to包括Bitstreamand clickOK。这将为软件开发工具-Vivado SDK的系统包装器导出硬件设计。



A new file directory will be created underHello_World.SDKsimilar to the Vivado hardware design project name. Two other files,。sysdefand。hdf也是创建的。此步骤本质上创建了一个新的SDK工作区。

8.2) On the main toolbar, clickFileand thenLaunch SDK。Leave both of the dropdown menus as their defaultLocal to Projectand clickOK。这将打开Xilinx SDK并导入您的硬件。

9.1) Click the New下拉箭头并选择xilinx→申请项目。



Give your project a name that has no empty spaces and clickNext。

9.2) Select你好世界from the list of templates and clickFinish。

You will see two new folders in theProject Explorer控制板。

• 你好世界which contains all the binaries, .C and .H (Header) files
• 你好世界_bsp这是董事会支持文件夹

你好世界is our main working source folder. This also contains an important file shown here which is the “lscript.ld”. This is a Xilinx auto generated linker script file. Double click on this file to open.

9.3）回到Project Explorer，双击并打开Helloworld.Cunder thesrc文件夹。

This is the main .C file which will print “Hello World” in the console when executed.

10.1）确保BASYS 3通过USB-JTAG端口打开并连接到主机PC-此端口将作为与微封面的USB-UART连接双重目的。

On the top toolbar, click the 程序FPGA按钮。

10.2）单击程序to program your FPGA with your hardware design.

11.1）打开串行终端申请（Terra术语）。连接到Basys 3 UART端口，波特率为9600。可以通过双击uartlite块来改变您的块设计中的波特率。



11.2）带有TERA术语串行端口设置

12.1) Back in SDK, select your你好世界project and click the Run As…按钮。选择在硬件（系统调试器）上启动and clickOK。

12.2) Your program will run and you should see “Hello World” pop up inside of your Serial Terminal. Hooray!