Nexys 4 DDR - Getting Started with Microblaze Servers
概述
本指南将使用Vivado IP集成符,提供基于微蓝光的硬件设计的逐步演练,该设计将在Getting Started with Microblazeguide by making use of the on-board Ethernet port and GPIOs for the Nexys 4 DDR FPGA board.
At the end of this tutorial you will have a comprehensive hardware design for Nexys4 DDR that makes use of various Hardware ports on the Nexys 4 DDR which are managed by the Microblaze Softcore Processor block.
Prerequisites
Hardware
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数字Nexys 4 DDR FPGA Board
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Micro USB Cable
Software
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Xilinx Vivado 2015.X with the SDK package
Board Support Files
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Board Support Files
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These files will describeGPIO接口板和更容易选取ect your FPGA board and addGPIOIP blocks.
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Follow this Wiki guide (Vivado Board Files for Digilent 7-Series FPGA Boards)如何为Vivado安装板支持文件。
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Important!
在Vivado版本2019.1之后,Xilinx将以太网PHY MII贬低为MII(MII2RMII),而无需直接替换。通过从Vivado 2019.1或更早的安装中获取IP源的副本,该核心仍然可以在较新版本中使用。您可以在2019.2上包括IP源,就像常规的IP存储库一样。这个线程, from the Xilinx support forum, has additional information on the workaround.
Introduction
Microblaze是Xilinx的软IP核心,它将完全在Xilinx FPGA通用记忆和逻辑结构中实现微处理器。对于本教程,我们将添加以太网功能并创建Echo服务器。
General Design Flow
I. Vivado
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打开Vivado并选择在下4 DDR董事会
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Create an new Vivado Project
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Create empty block design workspace inside the new project
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使用IP集成器工具添加所需的IP块并构建硬件设计
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Validate and save block design
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Create HDL system wrapper
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运行设计综合和实施
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Generate Bit File
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Export Hardware Design including the generated bit stream file to SDK tool
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Launch SDK
Now the Hardware design is exported to the SDK tool. The Vivado to SDK hand-off is done internally through Vivado. We will use SDK to create a Software application that will use the customized board interface data and FPGA hardware configuration by importing the hardware design information from Vivado.
II. SDK
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创建新的应用程序项目并选择默认Hello World模板
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Program FPGA
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跑configuration by selecting the correct UART COM Port and Baud Rate
Tutorial
1.创建一个新项目
1.4) If you have followed the Board Support File Wiki guide then click next and selectBoards。From the filter options make required selections for Vendor, Display Name and Board Revision.Nexys 4 DDRshould be displayed in the selection list. A mismatch in selecting the correct board name will cause errors.
At this point you have successfully created a project that will properly communicate with the Nexys 4 DDR.
2. Creating New Block Design
2.1) This is the main project window where you can create a IP based block design or add RTL based design sources. The flow navigator panel on the left provides multiple options on how to create a hardware design, perform simulation, run synthesis and implementation and generate a bit file. You can also program the board directly from Vivado with the generated bit file for an RTL project using the Hardware Manager. For our design, we will use the IP Integrator to create a new block design.
添加微型封面核心:
添加必要的输出时钟:
3. Adding the IP Cores
3.1) We will now add all of the necessary IP blocks to our project. There are 4 cores we will add:* Memory Interface Generator * Ethernet PHY MII to Reduced MII * AXI Uartlite * AXI EthernetLite * AXI Timer
4. Configuring and Routing the IP Cores
4.1) Click跑Block Automationand run it for the mig_7series_0 block.
When the MIG block automation is run, you will see this specific error message [BD 41-1273]. You can ignore this for now. It will not affect your design in any way. The MIG block will be configured as per the board support files that have been downloaded for the Nexys 4 DDR. ClickOK至dismiss this message.
4.14)打开您的新约束文件并粘贴其中的以下代码:
set_property -dict {package_pin d5 iostandard lvcmos33} [get_ports {eth_ref_clk}];#sch = eth_ref_clkSave the xdc file when you are finished.
5. Exporting Hardware Design to SDK
6. Launching SDK
7. Inside SDK for Vivado
7.1) A new window for SDK will open. The HW design specification and included IP blocks are displayed in thesystem.hdf文件。SDK工具独立于Vivado,即从这一点开始,您可以在导出的HW Design以C/C ++中创建SW项目。如有必要,您还可以直接从主Vivado Project目录中创建的SDK文件夹启动SDK。
现在,如果您需要返回Vivado并更改HW设计,则建议关闭SDK窗口并在Vivado进行所需的HW设计编辑。此后,您必须遵循创建新的HDL包装器的顺序,保存设计和BIT文件生成。然后必须将此新的位文件和系统包装器导出到SDK。
Since we do not have any HW design edits at this point, we will proceed with creating a software application to run an echo server.
8. Creating New Application Project in SDK
8.1) Go toFile→New→Application Projectin the main toolbar. A new project window will pop up. Give your SDK project a name that has no empty spaces as shown below. Make sure theTarget Hardwareis the correct hardware design. In our case, it will bedesign_1_wrapper_hw_platform_0。
If for example, you also have another hardware design in the项目资源管理器window, then you will also see this design name in the Target Hardware drop down selection list.
Since we only have one hardware designdesign_1_wrapper_hw_platform_0this will be our target hardware. SelectCreate NewunderBoard Support Package。该工具将自动填充Board Support Packagename to match with the give project name. Click下一个。
8.3) After completing the previous step, you will see two new folders in the项目资源管理器panel.echo_serverwhich contains all the binaries, .C and .H (Header) files, andecho_server_bspwhich is the board support folder.
echo_serveris our main working source folder. This also contains an important file shown here in the src folder calledlscript.ld。This is a Xilinx auto generated linker script file. Double click on this file to open.
9. Verify Linker Script File for Memory Region Mapping
9.1) In the linker script, take a look at theSection to Memory Region Mappingbox. If you did theMake DDR2 Externalstep then thetarget memory regioncolumn必须readmig_7series_0。
10. Setting PHY Link Speed
11. Programming FPGA with Bit File
12.设置SDK串行控制台并运行服务器
13.运行服务器
14. Testing the Server with Tera Term
14.1) Connect your PC to your Nexys 4 DDR using an Ethernet cable.如果使用路由器,请观看UART控制台以找出Nexys 4 DDR Echo服务器的IP,然后连接到该IP地址。将连接设置为静态是不必要的。
14.2) In order to connect to the echo server directly from your computer, you must set up your Ethernet connection with a static IP address. To do this:
14.2.5)单击使用以下IP地址:bullet and type in an IP address “192.168.1.XX”, where XX is a value between 2 and 255, but not 10.This IP must not be the same as another already on your network。Make sure to click within the子网掩码field to get the 255.255.255.0 mask to autofill. ClickOkand you will have a static IP address.