Nexys 4 DDR - Getting Started with Microblaze Servers

概述

本指南将使用Vivado IP集成符,提供基于微蓝光的硬件设计的逐步演练,该设计将在Getting Started with Microblazeguide by making use of the on-board Ethernet port and GPIOs for the Nexys 4 DDR FPGA board.

At the end of this tutorial you will have a comprehensive hardware design for Nexys4 DDR that makes use of various Hardware ports on the Nexys 4 DDR which are managed by the Microblaze Softcore Processor block.


Prerequisites

Hardware

  • 数字Nexys 4 DDR FPGA Board
  • Micro USB Cable

Software

  • Xilinx Vivado 2015.X with the SDK package

Board Support Files

Important!

在Vivado版本2019.1之后,Xilinx将以太网PHY MII贬低为MII(MII2RMII),而无需直接替换。通过从Vivado 2019.1或更早的安装中获取IP源的副本,该核心仍然可以在较新版本中使用。您可以在2019.2上包括IP源,就像常规的IP存储库一样。这个线程, from the Xilinx support forum, has additional information on the workaround.


Introduction

Microblaze是Xilinx的软IP核心,它将完全在Xilinx FPGA通用记忆和逻辑结构中实现微处理器。对于本教程,我们将添加以太网功能并创建Echo服务器。


General Design Flow

I. Vivado

  • 打开Vivado并选择在下4 DDR董事会
  • Create an new Vivado Project
  • Create empty block design workspace inside the new project
  • 使用IP集成器工具添加所需的IP块并构建硬件设计
  • Validate and save block design
  • Create HDL system wrapper
  • 运行设计综合和实施
  • Generate Bit File
  • Export Hardware Design including the generated bit stream file to SDK tool
  • Launch SDK

Now the Hardware design is exported to the SDK tool. The Vivado to SDK hand-off is done internally through Vivado. We will use SDK to create a Software application that will use the customized board interface data and FPGA hardware configuration by importing the hardware design information from Vivado.

II. SDK

  • 创建新的应用程序项目并选择默认Hello World模板
  • Program FPGA
  • 跑configuration by selecting the correct UART COM Port and Baud Rate

Tutorial

1.创建一个新项目

1.1) Open up Vivado and click创建新项目至open Vivado's New Project wizard.

1.2) A new window will open up, click下一个and you'll see the screen below. Name your project (no spaces!) and choose your project saving directory before clicking下一个。Underscores are a good substitute for empty spaces.

1.3) We will be building this project from the ground up and adding our own sources so we will want to create an RTL project. SelectRTL Project离开Do not specify sources盒子未选中。点击下一个

1.4) If you have followed the Board Support File Wiki guide then click next and selectBoards。From the filter options make required selections for Vendor, Display Name and Board Revision.Nexys 4 DDRshould be displayed in the selection list. A mismatch in selecting the correct board name will cause errors.

1.5)单击下一个, a summary of the new project design sources and target device is displayed. ClickFinish

At this point you have successfully created a project that will properly communicate with the Nexys 4 DDR.


2. Creating New Block Design

2.1) This is the main project window where you can create a IP based block design or add RTL based design sources. The flow navigator panel on the left provides multiple options on how to create a hardware design, perform simulation, run synthesis and implementation and generate a bit file. You can also program the board directly from Vivado with the generated bit file for an RTL project using the Hardware Manager. For our design, we will use the IP Integrator to create a new block design.

2.2) On the left you should see the Flow Navigator. SelectCreate Block Design在IP集成器下。在没有任何空的空间的情况下为您的设计命名。

添加微型封面核心:

2.3) An empty design workspace is created where you can add IP blocks. Click on the Add IPbutton. This should open a catalog of pre-built IP blocks from Xilinx IP repository. Search for “Microblaze” and double click on it to add the IP block to your empty design.

2.4) This is the Xilinx Microblaze IP block. When a new IP block is added the user can customize the block properties by either clicking on the跑Block Automationmessage prompt or by double clicking on the block itself.



2.5) Select跑Block Automation定制助手窗口将使用默认设置打开。设置如下图。


2.6) Running the block automation will auto-generate a set of additional IP blocks which will be added to our hardware design automatically based on the options selected in the previous step.Do not click on Run Connection Automation yet.

添加必要的输出时钟:

2.7)双击Clock Wizard(clk_wiz_1) IP block.

2.8) ChangeCLK_IN1使用“系统时钟”,并且ext_reset_in至use “reset” as shown below and clickOK。This will customize the block with our new user settings.

2.9) Select the输出时钟标签。

2.10) Enableclk_out2, andclk_out3。Setclk_out2至“200.0”MHz,clk_out3至“50.0”MHz,并设置Reset TypeasActive Low。左面板显示GUIrepresentation of the block and its internal settings. Observe that the reset pin will now read as重置n。完成后单击OK


3. Adding the IP Cores

3.1) We will now add all of the necessary IP blocks to our project. There are 4 cores we will add:
* Memory Interface Generator * Ethernet PHY MII to Reduced MII * AXI Uartlite * AXI EthernetLite * AXI Timer
3.2)一次将所有这些添加到您的设计中,一次使用 Add IPbutton. Once they are all added, you should see the four blocks shown below.


4. Configuring and Routing the IP Cores

4.1) Click跑Block Automationand run it for the mig_7series_0 block.



When the MIG block automation is run, you will see this specific error message [BD 41-1273]. You can ignore this for now. It will not affect your design in any way. The MIG block will be configured as per the board support files that have been downloaded for the Nexys 4 DDR. ClickOK至dismiss this message.

4.2)Axi以太网块, connect theMII output至theMII inputon the以太网PHY MII减少MII块。为此,将悬停在MII+旁边的蓝色矩形上,直到看到铅笔光标为止。单击并将其拖到另一个块的 +MII输入并释放。

4.2) Routeclk_out2andclk_out3on yourClocking Wizard块到sys_clk_ion the内存界面生成器andref_clkon theEthernet PHY MII to Reduced MIIblock respectively.

4.3) Click跑Connection Automation。取消检查微型闪电_0check-box and clickOK

4.4) Click再生布局(下面以蓝色盘旋),您的块设计应该像这样:

)
4.5)路线interrupton theAXI Timer块到in0 [0:0]on theConcatblock. Next routeip2intc_irpton theAXI EthernetLite块到in1 [0:0]on theConcatblock.

4.6) Connect重置non theClocking Wizard块到the重置pin.

4.7) Right click somewhere in the background (white space) of your design and clickCreate Port…, or use the shortcut, Ctrl-K. Name this port “eth_ref_clk” and change the options to the one in the picture below. ClickOKonce finished.

4.8)连接这个eth_ref_clkpin toref_clkon theEthernet PHY MII to Reducted MIIblock.

4.9)右键单击旁边的蓝色条纹矩形DDR2+bus on the内存界面生成器block and clickMake External

4.10) Clicking再生布局再次将为您的该项目提供最终的块设计布局。

4.11) We must now connect the eth_ref_clk pin to the correct pin on the FPGA by creating an XDC file. Under the设计nwindow, select theSources标签。Expand thecontraints文件夹,右键单击约束然后单击添加资源…

4.12) SelectAdd or create constraints然后单击下一个

4.13) ClickCreate File…, name your new contraints file and clickOKand thenFinish

4.14)打开您的新约束文件并粘贴其中的以下代码:
set_property -dict {package_pin d5 iostandard lvcmos33} [get_ports {eth_ref_clk}];#sch = eth_ref_clk

Save the xdc file when you are finished.

4.15) Now, right click on your design_1 block diagram and clickCreate HDL Wrapper。When the window pops up, select the让Vivado管理包装纸和自动更新bullet and clickOK

4.16) ClickGenerate Bitstreamat the top of the work space. This process will take a while.


5. Exporting Hardware Design to SDK

5.1)在窗口的左上角,从工具栏中单击File→Export Hardware。通过选中框,确保包含生成的Bitstream。这将为软件开发工具-Vivado SDK的系统包装器导出硬件设计。

There is currently a bug where thedownload.bitNexys 4 DDR板未生成文件。要解决此问题,请单击文件→导出→导出bitstream文件…然后导航到project/project.sdk/design_wrapper_hw_platform_0并导出一个名为“下载”的新位文件


6. Launching SDK

6.1)去File→Launch SDK然后单击OK。The SDK file created local to the Vivado design project location will be launched. The hand-off to SDK from Vivado is complete.


7. Inside SDK for Vivado

7.1) A new window for SDK will open. The HW design specification and included IP blocks are displayed in thesystem.hdf文件。SDK工具独立于Vivado,即从这一点开始,您可以在导出的HW Design以C/C ++中创建SW项目。如有必要,您还可以直接从主Vivado Project目录中创建的SDK文件夹启动SDK。

现在,如果您需要返回Vivado并更改HW设计,则建议关闭SDK窗口并在Vivado进行所需的HW设计编辑。此后,您必须遵循创建新的HDL包装器的顺序,保存设计和BIT文件生成。然后必须将此新的位文件和系统包装器导出到SDK。

Since we do not have any HW design edits at this point, we will proceed with creating a software application to run an echo server.


8. Creating New Application Project in SDK

8.1) Go toFile→New→Application Projectin the main toolbar. A new project window will pop up. Give your SDK project a name that has no empty spaces as shown below. Make sure theTarget Hardwareis the correct hardware design. In our case, it will bedesign_1_wrapper_hw_platform_0

If for example, you also have another hardware design in the项目资源管理器window, then you will also see this design name in the Target Hardware drop down selection list.

Since we only have one hardware designdesign_1_wrapper_hw_platform_0this will be our target hardware. SelectCreate NewunderBoard Support Package。该工具将自动填充Board Support Packagename to match with the give project name. Click下一个


8.2)选择IWIP回声服务器在可用模板的列表下,然后单击Finish

8.3) After completing the previous step, you will see two new folders in the项目资源管理器panel.echo_serverwhich contains all the binaries, .C and .H (Header) files, andecho_server_bspwhich is the board support folder.

echo_serveris our main working source folder. This also contains an important file shown here in the src folder calledlscript.ld。This is a Xilinx auto generated linker script file. Double click on this file to open.


9. Verify Linker Script File for Memory Region Mapping

9.1) In the linker script, take a look at theSection to Memory Region Mappingbox. If you did theMake DDR2 Externalstep then thetarget memory regioncolumn必须readmig_7series_0
9.2) Scroll down to check if this applies to all rows. If for any region it does not saymig_7series_0,然后单击下面的行Memory Regioncolumn and selectmig_7series_0


10.1)打开system.mssfile within theecho_server_bspfolder and clickModify this BSP's Settings

10.2) Once in董事会支持包设置select概述→standalone→lwip141。LWIP141库的配置表现在应在右侧可见。导航temac_adapter_options→phy_link_speed。Here you will need to changeCONFIG_LINKSPEED_AUTODETECTCONFIG_LINKSPEED100这样它看起来像下面的图片。


11. Programming FPGA with Bit File

11.1)确保通过Micro USB电缆打开Nexys 4 DDR并连接到主机PC。在主工具栏上,单击Xilinx工具→程序FPGA
Make sure that theHardware Platformis selected asdesign_1_wrapper_hw_platform_0

In the software configuration box, under小精灵文件以在块中初始化RAM列,行选项必须读取bootloop。If not, click on the row and selectbootloop

现在单击程序。

12.设置SDK串行控制台并运行服务器

12.1) Right click on theecho_serverproject folder and select跑As→Run Configurations

12.2) Go to theSTDIO Connectiontab and check theConnect STDIO to Consolecheck-box. ClickApply, then click


13.运行服务器

13.1) In the console window at the bottom of the screen the details of the connection will be displayed.


14. Testing the Server with Tera Term

14.1) Connect your PC to your Nexys 4 DDR using an Ethernet cable.如果使用路由器,请观看UART控制台以找出Nexys 4 DDR Echo服务器的IP,然后连接到该IP地址。将连接设置为静态是不必要的。
14.2) In order to connect to the echo server directly from your computer, you must set up your Ethernet connection with a static IP address. To do this:
14.2.1) Right click your internet connection and click打开Network and Sharing Center

14.2.2) Find the Ethernet Connection to your Nexys 4 DDR. It should be an unidentified network. ClickLocal Area Connection

14.2.3) Click特性

14.2.4) SelectInternet Protocol Version 4 (TCP/IPv4)然后单击特性

14.2.5)单击使用以下IP地址:bullet and type in an IP address “192.168.1.XX”, where XX is a value between 2 and 255, but not 10.This IP must not be the same as another already on your network。Make sure to click within the子网掩码field to get the 255.255.255.0 mask to autofill. ClickOkand you will have a static IP address.

14.3) Open Tera Term and type in the following info and clickOk

14.4) Type anything into the console and press your keyboard's Enter key. The echo server will echo back your input and display it in the console.

You can go to Setup→Terminal and change the settings below for a more traditional echo server format