nexys 4-从微型闪烁服务器开始

本指南将使用Vivado IP集成符，提供基于微蓝光的硬件设计的逐步演练，该设计将在开始使用微型布莱guide by making use of the on-board Ethernet port and GPIOs for the Nexys 4 FPGA board.

At the end of this tutorial you will have a comprehensive hardware design for Nexys4 that makes use of various Hardware ports on the Nexys 4 which are managed by the Microblaze Softcore Processor block.

• Xilinx Vivado with the SDK package

• Board Support Files. These files will describeGPIO在板上的接口，使选择FPGA板并添加更容易GPIOIP blocks.
  • Follow this Wiki guide (Vivado Board Files for Digilent 7-Series FPGA Boards) on how to install Board Support Files for Vivado 2014.4

• Digilent Nexys 4 FPGA Board and Micro USB Cable for UART communication and JTAG programming

Microblaze is a soft IP core from Xilinx that will implement a microprocessor entirely within the Xilinx FPGA general purpose memory and logic fabric. For this tutorial, we are going to add Ethernet functionality and create an echo server.

I. Vivado
* Open Vivado and select Nexys 4 board
*创建一个新的Vivado项目
*在新项目中创建空块设计工作区
* Add required IP blocks using the IP integrator tool and build Hardware Design
*验证并保存块设计
*创建HDL系统包装器
*运行设计合成和实施
* Generate Bit File
*导出硬件设计，包括生成的位流文件到SDK工具
*启动SDK

现在，硬件设计导出到SDK工具。Vivado到SDK交接是通过Vivado内部完成的。我们将使用SDK创建一个软件应用程序，该应用程序将通过从Vivado导入硬件设计信息来使用自定义的板接口数据和FPGA硬件配置。

ii。SDK
* Create new application project and select default Hello World template
* Program FPGA
* Run configuration by selecting the correct UART COM Port and Baud Rate

1.1）单击创建新项目。选择项目名称和位置，以便有no blank spaces。This is an important naming convention to follow for project names, file names and location paths.
Underscore in a good substitute for empty spaces.
It is good practice to have a dedicated folder for Vivado Projects, preferably with the smallest possible path length. Example: C:/Vivado_Projects.



命名您的项目并选择项目位置，然后单击“下一步”。

1.2) Choose Project Type as RTL Project. Leave the - do not specify sources box unchecked and click next.

1.3) If you have followed the Board Support File Wiki guide then click next and selectBoards。
从过滤器选项中，对供应商，显示名称和董事会修订版进行了必要的选择。
Nexys 4should be displayed in the selection list. A mismatch in selecting the correct board name will cause errors.

1.4）单击下一步，然后完成，Vivado将为您创建一个项目。

2.1）通过单击下面以蓝色圆圈的按钮来创建块设计。

3.1）首先单击“添加IP”按钮在下面盘旋为蓝色。搜索“微型闪电”and double click the IP highlighted below.

3.2）单击“运行块自动化”以蓝色圈出，然后更改选项以匹配下图中的选项。单击“确定”。

4.1) Double-click the Clocking Wizard block highlighted below, and set CLK_IN1 to use “sys_clock” and EXT_RESET_IN to use “reset”.

4.2) Select the Output Clocks tab and enableclk_out2。Setclk_out2to50MHz。These will clock the memory controller and the Ethernet Reference clock, respectively.
将重置类型设置为Active Lowusing the bullets below. When you are finished, click Ok.



您的块设计应该看起来像这样：

5.1) We will now add all of the necessary IP blocks to our project. There are 5 cores we will add:
* AXI EMC
* AXI Uartlite
* Ethernet PHY MII to Reduced MII
* AXI EthernetLite
* AXI Timer
Add all of these to your design, one at a time, using the“添加IP”button. Once they are all added, you should see the five blocks shown below.

6.1) On theAxi EMC块，连接RDLK输入到clk1 output在Clock wizard block。To do this, hover over the blue rectangle next to EMC rdclk until you see a pencil cursor. Click and drag this over to the clk1 output of the other block and release.

6.2）在Axi以太网块，连接MII output到MII input在Ethernet PHY MII to Reduced MII block。To do this, hover over the blue rectangle next to MII+ until you see a pencil cursor. Click and drag this over to the +MII input of the other block and release.

6.3）单击“运行连接自动化”。取消检查Microblaze_0check-box and click OK.

6.4) Click再生布局(circled in blue below), and your block design should look like this:

6.5）
* Routeinterrupt在AXI Timerblock toin0 [0：0]在Concatblock.
* Routeip2intc_irpt在AXI EthernetLiteblock toIn1[0:0]在Concatblock.




* Connect重置在Clocking Wizard块到达重置别针。

6.6）右键单击设计的背景（空白空间），然后单击Create Port…, or use the shortcut, Ctrl-K. Name this port eth_ref_clk and change the options to the one in the picture below.

6.7) Connect thiseth_ref_clkpin toref_clk在以太网PHY MII减少MIIblock. Then Connect both to the output pin clk_out2 from the clock wizard.

6.8) Double click into theAxi EMC块，选择内存库1，设置如下所示。

6.9）单击地址edditor选择S_AXI_MEM，然后将范围更改为16m。

6.10) Clicking再生布局again will result in your final block design layout for this project.

6.11) We must now connect the eth_ref_clk pin to the correct pin on the FPGA by creating an XDC file. Under theDesignwindow, select the来源标签。扩展contraintsfolder, right click onconstr然后单击“Add Sources…”

6.12) Select Add or create constraints and click Next.

6.13）单击Create File…，命名您的新对构造文件，然后单击“确定”，然后完成。

6.14) Open your new constraints file and paste the following line of code in it:
set_property -dict { PACKAGE_PIN D5 IOSTANDARD LVCMOS33 } [get_ports { eth_ref_clk }];
Save the xdc file when you are finished.

6.15）现在，右键单击您的Design_1框图，然后单击“Create HDL Wrapper”。窗口弹出时，选择“让Vivado管理包装器和自动更新”子弹，然后单击“确定”。

6.16) Click “Generate Bitstream” at the top of the work space. This process will take a while.

7.1) On the top left corner of the window, from the tool bar click onFileand select导出硬件。
这将为软件开发工具-Vivado SDK的系统包装器导出硬件设计。
Make sure the generated bitstream is included by checking the box。

8.1) Go toFileand select启动SDK然后单击OK. The SDK file created local to the Vivado design project location will be launched. The hand-off to SDK from Vivado is complete.

9.1）SDK的新窗口将打开。HW设计规范和随附的IP块显示在system.hdf文件。独立于Vivado SDK工具,即this point, you can create your SW project in C/C++ on top of the exported HW design. If necessary, you can also launch SDK directly from the SDK folder created in the main Vivado Project directory.
现在，如果您需要返回Vivado并更改HW设计，则建议关闭SDK窗口并在Vivado进行所需的HW设计编辑。此后，您必须遵循创建新的HDL包装器的顺序，保存设计和BIT文件生成。然后必须将此新的位文件和系统包装器导出到SDK。
Since we do not have any HW design edits at this point, we will proceed with creating a software application to run an echo server.

10.1）去Filein the main tool bar and selectNew » Application Project。将弹出一个新的项目窗口。
Give your SDK project a name that has no empty spaces as shown below. Make sure the目标硬件is the correct hardware design. In our case, it will be “design_1_wrapper_hw_platform_0”.
If for example, you also have another hardware design in the项目资源管理器window, then you will also see this design name in the Target Hardware drop down selection list.
Since we only have one hardware designdesign_1_wrapper_hw_platform_0this will be our target hardware. SelectCreate NewunderBoard Support Package。The tool will automatically populate theBoard Support Package名字匹配给项目name.
点击Next.



SelectIWIP回声服务器under the list of available templates and click Finish.

10.2) After completing the previous step, you will see two new folders in the项目资源管理器panel.
echo_serverwhich contains all the binaries, .C and .H (Header) files
echo_server_bspwhich is the board support folder
echo_serveris our main working source folder. This also contains an important file shown here in the src folder called “lscript.ld”. This is a Xilinx auto generated linker script file. Double click on this file to open.

11.1）在链接器脚本中，看看Available Memory Regions盒子。这个名字应该是axi_emc_0_s_AXI_MEMO_BASEADDRand the Size should be 0x01000000

12.1）打开system.mss文件中的文件echo_server_bsp文件夹，然后单击Modify this BSP's Settings。



SelectLWIP140, then expand thetemac_adapter_optionsand findphy_link_speedin the list. Change the value ofphy_link_speedtoconfig_linkspeed100然后按确定。

13.1) Make sure that the Nexys 4 DDR is turned on and connected to the host PC with the provided micro USB cable. On the main toolbar, clickXilinx工具»程序FPGA
确保硬件平台is selected asdesign_1_wrapper_hw_platform_0。
In the software configuration box, under小精灵文件以在块中初始化RAM列，行选项必须读取bootloop。如果没有，请单击该行，然后选择bootloop。
Now click on Program.

14.1）右键单击echo_serverproject folder and select运行为»运行配置



Go to theSTDIO Connectiontab and check the将STDIO连接到控制台Check-Box。点击Apply，然后单击Run。

15.1) In the console window at the bottom of the screen the details of the connection will be displayed.

16.1）使用以太网电缆将PC连接到NEXYS4。

16.2) In order to connect to the echo server, you must set up your Ethernet connection with a static IP address.
去做这个：
* Right click your internet connection and clickOpen Network and Sharing Center。



* Find the Ethernet Connection to your Nexys4-DDR. It should be an unidentified network. ClickLocal Area Connection。



* Click特性。



* 选择Internet Protocol Version 4 (TCP/IPv4)然后单击特性。



* Click the使用以下IP地址：bullet and type in an IP address 192.168.1.XX, where XX is a value between 2 and 255, but not 10. Make sure to click within the子网掩码field to get the 255.255.255.0 mask to autofill. Click Ok and you will have a static IP address.

16.3) Open Tera Term and type in the following info and click Ok.

16.4）在控制台中键入任何内容，然后按Enter。ECHO服务器将回声回声您的输入并将其显示在控制台中。
您可以转到设置>终端，然后更改以下设置以获取更传统的Echo服务器格式