Nexys 4 - Getting Started with Microblaze

本指南将提供e a step by step walk-through of creating a Microblaze based hardware design using the Vivado IP Integrator for the Nexys 4 FPGA board.

At the end of this tutorial you will have:

• Created a Microblaze based hardware ( HW ) design in Xilinx Vivado

• Created a .C Project in Xilinx Vivado SDK ( Software Development Kit) to display Hello World using the hardware design shown in the previous step

• Displayed the final output on both the SDK console and Tera Term

• Digilent Nexys 4 FPGA Board and Micro USB Cable for UART communication and JTAG programming

• Xilinx Vivado 2016.X with the SDK package.

• Board Support Files
  • These files will describeGPIOinterfaces on your board and make it easier to select your FPGA board and addGPIOIP blocks
  • Follow this Wiki guide (Vivado Board Files for Digilent 7-Series FPGA Boards) on how to install Board Support Files for Vivado

Microblaze is a soft IP core from Xilinx that will implement a microprocessor entirely within the Xilinx FPGA general purpose memory and logic fabric. For this tutorial, we are going to add a Microblaze IP block using the Vivado IP Integrator tool.

In addition to the Microblaze IP block, we would also like to make use of the DDR2 SDRAM component on the Nexys 4 DDR. Therefore a MIG ( Memory Interface Generator ) IP block will be added to our design.

Finally, a UART ( universal asynchronous receiver/transmitter ) IP block will be added to communicate between the host PC and the soft processor core running on the Nexys 4 DDR.

I. Vivado

• Open Vivado and select Nexys 4 board
• Create an new Vivado Project
• Create empty block design workspace inside the new project
• Add required IP blocks using the IP integrator tool and build Hardware Design
• Validate and save block design
• Create HDL system wrapper
• Run design Synthesis and Implementation
• Generate Bit File
• Export Hardware Design including the generated bit stream file to SDK tool
• Launch SDK

Now the Hardware design is exported to the SDK tool. The Vivado to SDK hand-off is done internally through Vivado. We will use SDK to create a Software application that will use the customized board interface data and FPGA hardware configuration by importing the hardware design information from Vivado.

II. SDK

• Create new application project and select default Hello World template
• Program FPGA
• Run configuration by selecting the correct UART COM Port and Baud Rate

When you first run Vivado this will be the main start window where you can create a new project or open a recent one.

1.1) Click onCreate New Project. Choose the Project Name and Location such that there areno blank spaces. This is an important naming convention to follow for project names, file names and location paths. Underscore is a good substitute for empty spaces. It is good practice to have a dedicated folder for Vivado Projects, preferably with the smallest possible path length. Example: C:/Vivado_Projects. Name your Project and select the Project location and clickNext.

1.2) Choose Project Type asRTL Project. Leave theDo not specify sourcesbox unchecked and clickNext.

1.3) If you have followed the Board Support File Wiki guide then click next and selectBoards. From the filter options make required selections for Vendor, Display Name and Board Revision.Nexys 4should be displayed in the selection list. A mismatch in selecting the correct board name will cause errors.

1.4) A summary of the new project design sources and target device is displayed. ClickFinish.

2.1) This is the main project window where you can create a IP based block design or add RTL based design sources. The flow navigator panel on the left provides multiple options on how to create a hardware design, perform simulation, run synthesis and implementation and generate a bit file. You can also program the board directly from Vivado with the generated bit file for an RTL project using the Hardware Manager. For our design, we will use the IP Integrator to create a new block design.

2.2) On the left you should see the Flow Navigator. SelectCreate Block Designunder the IP Integrator. Give a name to your design without any empty spaces.

2.3) An empty design workspace is created where you can add IP blocks. Add an IP core by clicking on the Add IPicon. This should open a catalog of pre-built IP blocks from Xilinx IP repository. Search for “Microblaze” and double click on it to add the IP block to your empty design.

3.1) This is the Xilinx Microblaze IP block. When a new IP block is added the user can customize the block properties by either clicking on theRun Block Automationmessage prompt or by double clicking on the block itself.



3.2) SelectRun Block Automationand a customization assistant window will open with default settings.

3.3) Change default settings in the block options as shown below and clickOK. This will customize the block with our new user settings.

3.4) Running the block automation will auto-generate a set of additional IP blocks which will be added to our hardware design automatically based on the options selected in the previous step.Do not click on Run Connection Automation yet.

4.1) Double click on theClock Wizard(clk_wiz_1) IP block.

4.2) Choosesys clockfor CLK_IN1.

4.3) Select theOutput Clockstab.

4.4) SetReset TypeasActive Low. The left panel shows aGUIrepresentation of the block and its internal settings. Observe that the reset pin will now read asresetn. This graphically represents the internal setting for active low.

4.5) Now move to thePort Renamingtab. This will give you a summary of the inputs and outputs to the Clock Wizard IP block.ClickOKto finish block automation of Clock Wizard.Do not select Run Connection Automation yet.

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5.1) Go to Add IPand search for “UART”.

5.2) Select theAXI UartliteIP block.

5.3) This will add a UART block to the existing design. We need a UART controller to communicate between the terminal window on the Host-PC and the Nexys 4 hardware.

6.1) Now select theRun Connection Automationfrom theDesigner Assistancebar message prompt. This will open up the Run Connection Automation window. Select theext_reset_inas shown. A description of the interface will be shown along with available signal options. Selectresetas the board part interface.

6.2) Now select all available connections and clickOK. Completing this step will connect all the IP blocks that have been added and customized up to this point. In addition to performing auto-connection of available IP blocks, a new IP block calledmicroblaze_0_axi_periphwill be added to our design. Two signal pinsresetandsys_clockwill be added as well. The pin signals point to the right indicating that they are inputs to the clock wizard block ( clk_wiz_1) and reset clock wizard block ( rst_clk_wiz_1_100M).

6.3) Now select theRun Connection Automationfrom theDesigner Assistancebar message prompt.Now select all available connections and clickOK.

6.4) Select the button circled in blue. This is the Regenerate Layoutoption that will re-arrange the IP blocks in the design.

7.1) Select Validate Design. This will check for design and connection errors.



7.2) After the design validation step we will proceed with creating a HDL System Wrapper.

8.1) As highlighted in this step, right click ondesign_1and selectCreate HDL Wrapper. Let Vivado manage the wrapper and selectOK.

8.2) A system wrapper file will be generated and a message will be displayed in the tcl console informing us that thewrapper.vfile has been generated.

9.1) In theFlow Navigatorpanel on the left, underProgram and Debugselect theGenerate Bitstreamoption. If you haven't already saved your design, you will get a prompt to save the block design.


9.2)代会的一些文件。这个工具will runSynthesisandImplementation. After both synthesis and implementation have been successfully completed, the actual bit file will be created. You will find a status bar of Synthesis and Implementation running on the top right corner of the project window.


9.3) After the bitstream has been generated, a message prompt may pop-up on the screen. You don't have to open the Implemented Design for this demo. Just click onCancel.

10.1) On the top left corner of the window, from the tool bar click onFileand selectExport Hardware.
This will export the hardware design with system wrapper for the Software Development Tool - Vivado SDK.Make sure the generated bitstream is included by checking the box.

10.2) A new file directory will be created underHello_World.SDKsimilar to the Vivado hardware design project name. Two other files,.sysdefand.hdfare also created. This step essentially creates a new SDK Workspace.
If you browse to the location on the drive where the Vivado project has been created, you will see that new folders have been created under SDK. See TCL Console message in the screen capture below. Now that the design has been exported to Software Development Kit (SDK) tool, the next step will be to launch the SDK tool.

11.1) Go toFileand selectLaunch SDKand click OK. The SDK file created local to the Vivado design project location will be launched. The hand-off to SDK from Vivado is complete.

12.1) Go toFilein the main tool bar and selectNew Application Project. A new project window will pop up. Give your SDK project a name that has no empty spaces as shown below. Make sure theTarget Hardwareis the correct hardware design. In our case, it will bedesign_1_wrapper_hw_platform_0.
If for example, you also have another hardware design in theProject Explorerwindow, then you will also see this design name in the Target Hardware drop down selection list.
Since we only have one hardware designdesign_1_wrapper_hw_platform_0this will be our target hardware. SelectCreate NewunderBoard Support Package. The tool will automatically populate theBoard Support Packagename to match with the give project name.
Click Next.

13.1) SelectHello WorldunderAvailable Templateson the left panel and click Finish.

13.2)在完成前面的步骤中,您将see two new folders in theProject Explorerpanel:

-display_hello_worldwhich contains all the binaries, .C and .H (Header) files
-display_hello_world_bspwhich is the board support folder

display_hello_worldis our main working source folder. This also contains an important file shown here which is thelscript.ld. This is a Xilinx auto generated linker script file. Double click on this file to open.

14.1) Make sure that the Nexys 4 DDR is turned on and connected to the host PC with the provided micro USB cable.
In the quick selection tool bar, you will find a symbol with a red arrow and three green square boxes. This clickable button is physically located under theSearchtab in the main tool bar.
Click on this symbol to open the Program FPGA window.
Make sure that theHardware Platformis selected asdesign_1_wrapper_hw_platform_0.
In the software configuration box, underELF File to Initialize in BlockRAMcolumn, the row option must readbootloop. If not, click on the row and selectbootloop.
Now click on Program.

15.1) After the FPGA has been successfully programmed with the bit file, from theProject Explorerpanel, right click on thedisplay_hello_worldproject folder which has been highlighted in the screen capture below.
At the bottom of the drop down list, selectRun Asand then selectlaunch on hardware.

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You can use any serial terminal you would like including the one on SDK. We use Tera Term. Refer to this linkhttp://en.wikipedia.org/wiki/Tera_Termto know what Tera Term is. You can download and install Tera Term from this linkhttp://ttssh2.sourceforge.jp/index.html.en

16.1) Establish a serial connection with the correct communication port inside Tera Term.
Go toSDK Run Configurations→ Apply and Run.
Tera Term will work as a Console by displaying the output.
Notice that inside the built-in console window of SDK, there is a message displayed that readsPort COM4 is already in useindicating that theCOM4port is in use by Tera Term.