Use Flip-flops to Build a Clock Divider

A flip-flop is an edge-triggered memory circuit. In this project, we will implement a flip-flop behaviorally using Verilog, and use several flip-flops to create a clock divider that blinks LEDs.

Memory Circuits

• 有Xilinx ISE WebPACK安装。
• Set up your FPGA board.
• Be able to describe a digital circuit using logic operators.
• Be able to write test bench and simulate circuits using ISim.
• Be able to model and simulate a circuit delay.

• Xilinx ISE WebPACK.
• Adept 2

• Xilinx ISE compatible board such asNexys 4,Nexys 3,Nexys 2,Basys 3, orBasys 2

A D flip-flop (D-FF) is one of the most fundamental memory devices. A D-FF typically has three inputs: a data input that defines the next state, a timing control
input that tells the flip-flop exactly when to “memorize” the data input, and a reset input that can cause the memory to be reset to '0' regardless of the other two inputs (usually referred as asynchronous reset). Figure 1 below displays the block diagram for a D-FF.

D Flip-flop (DFF)

In this step, we are going to implement a D-FF with asynchronous reset.

As the block diagram in Fig. 1 shows, D flip-flops have three inputs: data input (D), clock input (clk), and asynchronous reset input (rst, active high), and one output: dataoutput(Q).

module dff(input D, input clk, input rst, output Q);

To describe the behavior of the flip-flop, we are going to use an “always” block. On the contrary to combinational circuits, the output of flip-flop changes when a rising edge or falling edge of clock occurs or the reset is asserted. In other words, output Q is sensitive to clock signalclkand reset signalrst. So we can describe the circuit as follows: always at rising edge ofclkor rising ofrst, if rst is asserted, Q is driven to logic '0', else Q is driven by D. In Verilog code:

always@(posedge(clk), posedge(rst))beginif(rst==1)Q<=1'b0;elseQ<=D;end

所以最终的Verilog实现D-FF看s as follows:

`timescale 1ns/1ps module dff(input D, input clk, input rst, output Q);always@(posedge(clk), posedge(rst))beginif(rst==1)Q<=1'b0;elseQ<=D;endendmodule

A clock signal is needed in order for sequential circuits to function. Usually the clock signal comes from a crystal oscillator on-board. The oscillator used on Digilent FPGA boards usually ranges from 50MHzto 100MHz; however, some peripheral controllers do not need such a high frequency to operate.

There is a simple circuit that can divide the clock frequency by half. The circuit is shown in Fig. 2 below:

Assumeclkdivis high initially. Asdininverts the signal clkdiv,dinis initially low. When the first rising edge of clock arrives,clkdivis updated by the currentdinvalue and changes to '0'. As soon as theclkdivchanges to '0',dinwill be pulled up to logic '1' by the inverter. When the next rising edge ofclkoccurs,clkdivwill change to logic '1' anddinwill change back to '0' after the propagation delay of the inverter. The waveform of the circuit in Fig. 2 above is shown on the right. As a result, the period ofclkdiv(the time between two adjacent rising edges) doubles the period ofclk(i.e., the frequency ofclkdivis half of theclkfrequency).

With this circuit, we can actually divide the clock by cascading the previous circuit, as displayed in Fig. 3 below:

Each stage divided the frequency by 2. Suppose that the input clock frequency to the first stage is 100MHz(1,000,000Hz). After the first stage, the frequency became $ \frac{100MHz}{2}\ = 50 MHz $. After the second stage, the frequency became $ \frac{100MHz}{2.2}\ = 25 MHz $. After n stage, the frequency became:

$$ \frac{100MHz}{\underbrace{2\cdot 2 \cdot \ldots \cdot 2}_\text{n}} = \frac{100,000,000}{2^n}Hz $$

The block diagram of the clock divider is shown in Fig. 4. We name the internal wire out of the flip-flopclkdivand the wire connecting to the input of D-FF din. The frequency of eachclkdivis shown in red.

In this diagram, we need two inputs: on-board clock inputclk, and a push-button as reset signalrst. we have one output to blink anLED, so let's call itled.

module clk_divider(input clk, input rst, output led);

We need to declare all the internal wires we are going to use.

wire[26:0]din;wire[26:0]clkdiv;

We need to instantiate 27 flip-flops with 27 inverters to divide the clock frequency by $2^27$ to 0.745Hz. To instantiate the first flip-flop with an inverter, the Verilog code should be as follows:

dff dff_inst0(.clk(clk), .rst(rst), .D(din[0]), .Q(clkdiv[0]));

For the rest 26 flip-flops, you can copy the code above 26 times and change the names of the internal wire each port will map to. However, we can also use generate statement with aforloop in Verilog to generate the code for us. By observing the block diagram shown above in Fig. 3, starting from the second flip-flop,rstport of D-FF is always connected to signal rst. If the port D is connected to signaldin[i], thenclkport is connected toclkdiv[i-1]and Q port is connected toclkdiv[i]. So, we can generate the 26 D-FF as follows:

genvar i; generate for (i = 1; i < 27; i=i+1) begin : dff_gen_label dff dff_inst ( .clk(clkdiv[i-1]), .rst(rst), .D(din[i]), .Q(clkdiv[i]) ); end endgenerate;

We can use the same generate statement to instantiate 27 inverters, or by observing the connections, the busdinis actually the inverse of busclkdiv. So, instead of writing the generate statement, we can simply write one assign statement as follows:

assign din=~clkdiv;

Connect the output of the flip-flop in the final stage toled.

assign led=clkdiv[26];

So the Verilog file of the design should be as follows:

`timescale 1ns/1ps module clk_divider(input clk, input rst, output led);wire[26:0]din;wire[26:0]clkdiv;dff dff_inst0(.clk(clk), .rst(rst), .D(din[0]), .Q(clkdiv[0]));genvar i;generatefor(i=1;i<27;i=i+1)begin:dff_gen_label dff dff_inst(.clk(clkdiv[i-1]), .rst(rst), .D(din[i]), .Q(clkdiv[i]));endendgenerate;assign din=~clkdiv;assign led=clkdiv[26];endmodule

As with the combinational circuit we have designed in previous projects, you can draft a test bench to test the circuit out before implementing it on-chip. However, in this test bench, we need to emulate the clock signal and the rst signal. The clock signal is actually a constantly oscillating signal. Using the Nexys 3 as an example, the input clock frequency is 100MHz, i.e., the period of the clock is 10 ns. Half of the period the clock is high, half of the period clock is low. In other words, every half of the period, 5 ns in this case, the clock will flip itself. To simulate the clock signal, instead of putting it in the initialize statement, we will use an always statement.

`timescale 1ns/1ps ... reg clk;always#5 clk = ~clk;

In the initialize block, we will initializeclksignal to 0 and holdrsthigh for 10ns to reset the clock divider. So, the Verilog Test Bench will look like this:

`timescale 1ns/1ps module tb;//Inputs reg clk;reg rst;//Outputs wire led;//Instantiate the Unit Under Test(UUT)clk_divider uut(.clk(clk), .rst(rst), .led(led));always#5 clk = ~clk;initialbegin//Initialize Inputs clk=0;rst=1;#10 rst = 0;//Wait100nsforglobal resettofinish#100;endendmodule

The simulated waveform is shown in Fig. 5 below. You can see in the waveform thatclkdiv[0]is half of the frequency ofclk, and thatclkdiv[1]is half of the frequency ofclkdiv[2].

Now you can create a UCF file that maps clk to the global clock on board, rst to a push button, and led to an on-boardLED. If your board has a 100MHzclock, you can see that theLEDblinks once every 1.45 seconds.

Now that you've completed this project, try these modifications:

1. Can you add two switches to control how fast theLEDblinks: Say, if switch[1:0] is 0,LEDblink frequency is 0.745Hz; if switch[1:0] is 1,LEDblink frequency is 1.49Hz; if switch[1:0] is 2,LEDblink frequency is 2.98Hz; if switch[1:0] is 3,LEDblink frequency is 5.96Hz.