在Vivado IPI设计中添加层次块

在Vivado，一个Hierarchical Blockis a block design within a block design. These blocks allow engineers to partition their designs into separate functional groups. This guide steps through the process of adding a pre-existing hierarchical block to a block design, recreating its example software application, and running the design in hardware.

Inventory

Guide

Setting Up Dependencies

检查Vivado-Library是否已经包含在Vivado项目中，如果不是，则应下载：

vivado-library-zmod-v1-2019.1-2.zip

那些熟悉GIT的人可能想克隆层次结构，而不是下载ZIP。下拉列表包含简短的说明。

使用git克隆层次结构
CD（令人难忘的地方）git克隆https://github.com/digilent/vivado-library -b zmod/v1/2019.1-2

Otherwise (if vivado-library is included in the project), use git tools to check out the branch:

Warning!如果IP从图书馆已经包含在project, checking out a different branch may cause changes to them. Be careful!

请注意，该命令选择的“分支”是一个已知与此文档一起使用的git标签。

cd (path)/vivado-library git checkout hierarchies

Adding a Hierarchical Block to a Hardware Design

1.

Launch Vivado, then open the Vivado Project the hierarchical block is to be used in, and open the project's Block Design.

Note:The design must contain a processor and a peripheral that can be used for stdout. In the case of Microblaze, a UART IP must be connected to the board's USBUART interface. In the case of Zynq, the PS UART is used by default.

完成Vivado IP积分器入门guide will result in a design that fits the requirements for using these hierarchical blocks.

2.

In Vivado's TCL Console, enter the following command:

source (path)/vivado-library/hierarchies/(hierarchy of choice)/create_hier.tcl

When the script is finished running, the block design will contain aHierarchical Block里面有几个IP。IP将相互连接，并连接到块的端口和引脚。可以通过使用“+” button.

3.

检查readme.txt文件，该文件可以在层次块的Vivado-library/层次结构中找到，以获取有关如何将层次结构端口连接到其余设计的其他信息。考虑到这些信息：

  1. Connect all of the hierarchical block's AXI interfaces to the processor in the design by clicking on运行连接自动化, and checking the appropriate boxes. These interfaces may appear more than once in the connection automation dialog. Select only one entry for each interface.
  2. Connect any interrupts the Hierarchy may have to the appropriate interrupt controller: an AXI Interrupt Controller IP (for Microblaze designs), the Zynq Processing System's irq_f2p port (for Zynq designs).
  3. 将任何其他时钟连接到由内存界面发生器或时钟向导（用于微闪烁设计）或Zynq处理系统（用于Zynq设计）产生的时钟。

4.

下一步约束层次结构的外部端口/s，有两个不同的工作流程：

  1. 如果在创建项目时选择了董事会板流can be used for this step.
  2. If a part was selected instead of a board, or the Board Flow cannot be used for whatever reason, the手动约束流应该使用。
4.1-创建外部PMOD端口

Open the dropdown for the chosen Workflow, below, and follow the instructions.

Note:这一步只是Pmod所需等级blocks. Zmod hierarchical scripts automatically create their external ports. For the purposes of this guide, consider the Zmod's external ports to have been created using the Manual Constraint Flow.

板流

去维瓦多的木板tab and select a Pmod connector to connect to the hierarchical block. Right click on the connector's entry, typically named something like “Connector JA”, and selectConnect Board Component。In the popup window, under连接到现有的IP，选择层次结构的PMOD桥IP的“ PMOD_OUT”接口。点击OK。

手动约束流

Select the Pmod_out port, then right click on it and select使外部。在设计中选择新创建的外部接口端口（命名为“ PMOD_OUT_0”），并给它一个令人难忘的名称。

4.2-验证设计并创建包装纸文件

无论选择哪种工作流程，）并保存。
Then create an HDL wrapper file, if one doesn't already exist, by right clicking on the design in the来源pane and selecting “Create HDL Wrapper”.

4.3 - Constraining the Design

This step works a little differently depending on whether the peripheral targeted by the hierarchical block is aZmod或aPmod。Select the dropdown for the chosen peripheral:

Pmod

如果是板流was chosen, open the README.txt file in the hierarchical block's folder in vivado-library-hierarchies to determine whether any additional constraints are required. If there are none,skip the rest of this section。

创建层次结构时，将一个名为“（层次结构名称）_pmod_out.xdc”的约束文件导入到Vivado项目中。该文件包含一个用于所有必需约束的模板，而不论所使用的流程如何。现在从来源pane, by finding it underConstraintsand double clicking on it.

Constraints required for the板流are left uncommented by default.

如果是手动约束流was chosen, uncomment any commented out lines that start with “set_property”, by removing the “#” symbol at the start of each of these lines.

The text “FIXME” is used in the constraint file to indicate places where values specific to the board and design must be manually entered.

在这些层次结构中，两种类型的手动输入值是约束文件的典型特征：

端口名称：
这些修复程序以文本“ get_ports”为之后。可以通过查看步骤5.1中创建的HDL包装器文件来找到这些修复程序的正确值。查找连接到HDL包装器端口映射中层次结构的PMOD_OUT接口端口的名称。将这些名称输入层次结构约束文件中的相应位置。

Location Constraints:
这些修复程序以文本为“ package_pin”之后，仅在手动约束流。The correct values for these FIXMEs can be found by reviewing the master XDC file for the target board. Master XDC files for Digilent boards can be found in thedigilent-xdcgithub上的存储库。查找与层次块的PMOD_OUT端口相对应的PMOD连接器的LOC属性值。将这些值输入层次结构约束文件中的相应位置。

Zmod

When create_hier.tcl is run for a Zmod Hierarchical Block, a constraint file is imported which contains template constraints for each external port created by the script. The constraint file is named after the hierarchical block created by the script, followed by the name of the particular Zmod, for example: “ZmodADC_0_ZmodADC.xdc”. The constraint file can be found under the Constraints section of Vivado IP Integrato's Sources pane.

在写作时，每个ZMOD层次结构块为Eclypse Z7的ZMOD端口中的每个端口提供了模板约束。默认情况下，zmodADCis connected to the Eclypse Z7's Zmod Port A, and the ZmodDACis connected to Zmod Port B. To connect to a different port, the user need only comment out the section of the xdc corresponding to the default port, and uncomment the section corresponding to the chosen port.

For other boards, the user must replace the PACKAGE_PIN location constraints for the Zmod ports with the corresponding locations found in the chosen board's master XDC file, which can be obtained through thedigilent-xdcgithub上的存储库。

5.

点击Generate Bitstream。根据项目的复杂性，此过程可能需要一些时间。

Baremetal软件

Zmod Hierarchical Blocks are supported in software by the Zmod Library. If using a Zmod, see theZmod Base Library User Guide, and skip the rest of this guide. If Petalinux support for the added hierarchy is desired, first see theZmod Petalinux Configuration Guide

1.

通过选择硬件设计和bitstream将其导出到SDKFile → Export → Export Hardwarein the menu bar at the top of the window. In the resulting pop up window, check theInclude bitstreambox, then clickOK。

2.

Launch Xilinx SDK by selectingFile → Launch SDKin the menu bar at the top of the window. Make sure to set the是上面步骤7中选择的相同位置。

3.

使用“空应用程序”模板创建一个新的应用程序项目。确保检查层次块是否需要对项目设置进行任何更改，或者是否必须将任何库添加到BSP中。这些要求（如果有）（如果有的话）在Vivado-library-library层次结构文件夹中的层次块的sdk_sources文件夹中的readme.txt文件中详细介绍。

4.

Copy all of the files from the selected hierarchical block's sdk_sources folder (in the vivado-library-hierarchies folder), then paste them into the application project's src folder.

5.

Make sure that the development board's programming mode select jumper is set to JTAG. Plug the board into the computer via its microUSB programming port and power it on.

Connect the SDK Terminal to the port associated with the board. The绿色按钮在串行终端中，窗格用于启动Connect to a serial portdialog. By default, the baud rate is 115200 for Zynq, and 9600 for Microblaze (when using the AXI Uartlite IP). If desired, other terminals, such as Tera Term or PuTTY, may be used instead.

6.

通过选择FPGA编程Xilinx → Program FPGA从Xilinx SDK的顶部菜单栏。

Once the FPGA is programmed, run the application project by right-clicking on the application project and selecting运行→在硬件（系统调试器）上运行。

通过演示应用程序打印的消息可以在串行终端中看到。

下一步

Now that the hierarchical block's example design is running, modifications can easily be made to the hardware or software.

设置了带有层次块的SDK源，以便可以轻松地将它们包含在任何使用该块的设计中。SDK_Sources下方的子文件夹包含该块的所有必要驱动程序。

For more reference materials and guides on the Digilent products being used, navigate to their resource centers, here on theDigilent Wiki。

For technical support, please visit theDigilent论坛。