Zedboard LED Demo

This guide will provide a step by step walk-through of importing a custom IP into Vivado and getting started in Xilinx SDK.

在本教程结束时，您将拥有：

• Imported and implemented a custom DigiLEDs IP block into the design.

• Created .C Project in Xilinx Vivado SDK ( Software Development Kit) to interface with the Zedboard.

• Familiarity with Vivado
• Block Design Experience

• Digilent Zedboard Board
• Micro USB Cable
  • Used for UART communication and JTAG programming
• Programmable RGB LEDs (WS2812, Neopixels)
  • Data-in Signal wire connected to Zedboard's JB1

• Xilinx Vivado 2016.2 with the SDK package.
  • Follow this Wiki guide (Installing Vivado) on how to install and activate Vivado

• Zedboard Support Files
  • These files will describeGPIOinterfaces on your board and make it easier to select your FPGA board and addGPIOIP blocks.
  • Follow this Wiki guide (Vivado Board Files for Digilent 7-Series FPGA Boards) on how to install Board Support Files for Vivado.

• 数字自定义IP： ZIP
• main.c file:ZIP

In this tutorial, we are going to add our own custom IP block into the base system design to be used with some programmable RGB LEDs.

I. Vivado

• 开放vivado
• 创建一个新的块设计
• Add the Zynq core IP and automate it
• Add the DigiLEDs custom IP to the project's IP repository
• Add the DigiLEDs IP to the design and configure it.
• Validate and save block design
• Create HDL system wrapper
• Run design Synthesis and Implementation
• Generate Bit File
• Export Hardware Design including the generated bit stream file to SDK tool
• Launch SDK

Now the Hardware design is exported to the SDK tool. The Vivado to SDK hand-off is done internally through Vivado. We will use SDK to create a Software application that will use the customized board interface data and FPGA hardware configuration by importing the hardware design information from Vivado.

II. SDK

• Create new application project and select Empty Application template
• Import main.c
• Program FPGA

当您第一次运行Vivado时，这将是您可以创建新项目或打开最近一个项目的主要开始窗口。

1.1) Click onCreate New Project。



1.2) You will be presented with the project creation wizard. ClickNext。



Next choose the Project Name and Location such that there areno blank spaces。This is an important naming convention to follow for project names, file names and location paths.
Underscore in a good substitute for empty spaces.

It is good practice to have a dedicated folder for Vivado Projects, preferably with the smallest possible path length. Example: C:/Vivado_Projects.

1.3) Name your Project and select the Project location and clickNext。



1.4) SelectRTL项目and clickNext。



1.5) This demo does not use any existing sources, existing IP or constraints. Click through the next three screens.

1.6) SelectBoardsand select theZedboardboard file. ClickNextand then结束。

2.1) Once the process has completed, clickCreate Block Designin the flow navigator.



2.2) Click好的。



2.3）空白块设计将打开。

3.1) Find and click“Project Settings”在Vivado左侧的项目经理下。

3.2) Within project settings, click “IP” on the left side. Then click the “Repository Manager” tab and click the + button (Highlighted below).

3.3) Navigate to your projects folder and select the“DigiLED-master”folder.

3.4) Verify that the new repo is in the list and click OK to exit project settings.

4.1) Click the “Add IP”按钮。在搜索框输入“DigiLED”和房子e click“ digiled_v1.0”。This will add our custom IP to the block design.

4.2) Click “Add IP”button again. This time type “Zynq” in the search box and double clickZYNQ7 Processing System。



This will add the Zynq processor to our block design.

4.3）单击“Run Block Automation”and click好的to auto configure the Zynq core.

4.4）单击运行Run Connection Automationand click好的to connect the DigiLED to the Zynq core.

5.1) Find theDigiLED_0块并双击块以自定义。

5.2) Select theHSVBullet and change the Number of LEDs field to the number of LEDs on your RGB引领strip before clicking OK.

6.1) Right click within your block design and click“Create Port”

6.2) Name the port “led_pin” and set it as anOutput。单击确定。

6.3) Connect the “led_pin” to “led_out” on the DigiLED_0 block using your cursor (It will look like a pencil).

6.4）在块设计的左侧，选择Sources选项卡，然后右键单击窗口。选择Add Sources…and a window will open. SelectAdd or create constraintsand clickNext。



Create a new file，确保名称具有no spaces, and click结束。

6.5）在“源”窗口中，打开约束文件夹以查找您的新.xdc文件。打开它。

6.6) Copy the line below, and paste it within pins.xdc. This is the pin connected to Connector JB1.

set_property -dict { PACKAGE_PIN W12 IOSTANDARD LVCMOS33 } [get_ports { led_pin }];

6.7) Save pins.xdc and close it.

6.8) Right clicksystem.bdand clickCreate HDL Wrapper…

7.1) In the top toolbar, click生成bitstream。如果您尚未保存设计，则将获得提示来保存块设计。

7.2) After the bitstream has been generated, a message prompt will pop-up on the screen. You don't have to open the Implemented Design for this demo. Just click on Cancel.

8.1) On the top left corner of the window, from the tool bar click on文件and selectExport Hardware。

This will export the hardware design with system wrapper for the Software Development Tool - Vivado SDK.

Make sure the generated bitstream is included by checking the box。

9.1) Go to文件and selectLaunch SDKand click OK. The SDK file created local to the Vivado design project location will be launched. The hand-off to SDK from Vivado is complete.

10.1）SDK的新窗口将打开。HW设计规范和随附的IP块显示在system.hdffile. SDK tool is independent of Vivado, i.e. from this point, you can create your SW project in C/C++ on top of the exported HW design. If necessary, you can also launch SDK directly from the SDK folder created in the main Vivado Project directory.

Now, if you need to go back to Vivado and make changes to the HW design, then it is recommended to close the SDK window and make the required HW design edits in Vivado. After this you must follow the sequence of creating a new HDL wrapper, save design and bit file generation. This new bit file and system wrapper must then be exported to SDK.

Since we do not have any HW design edits at this point, we will proceed with creating a software application.

10.2) On the left corner of the main SDK window, you will find theProject Explorerpanel. Notice that there is a main project folder under the namesystem_wrapper_hw_platform_0。

systemis the name of your block design created in Vivado. This hardware platform has all the HW design definitions, IP interfaces that have been added, external output signal information and local memory address information.

Say if at this point, you have closed SDK, made edits to your existing hardware design, and exported your design to SDK then after launching the SDK tool, you will find a new hardware platform called:system_wrapper_hw_platform_1除了旧的HW设计，即system_wrapper_hw_platform_0。

11.1) Go to文件在主工具栏中，选择New Application Project。A new project window will pop up.
Give your SDK project a name that has no empty spaces such as “DigiLEDs”. Make sure theTarget Hardwareis the correct hardware design. In our case, it will be “system_wrapper_hw_platform_0”. Click “Next”.

注意,错误地显示MicroBlaze形象s the processor type for this project. The processor will instead show ps7_cortexa9_0 for the Zedboard.

11.2) SelectEmpty ApplicationunderAvailable Templateson the left panel and click Finish.

11.3) After completing the previous step, you will see two new folders in theProject Explorerpanel.

**DigiLEDs** which contains all the binaries, .C and .H (Header) files **DigiLEDs_bsp** which is the board support folder

DigiLEDsis our main working source folder. This also contains an important file shown here which is the “lscript.ld”. This is a Xilinx auto generated linker script file.

12.1) Navigate to the “main.c” file.

12.2) Click and drag this main.c file into theDigiLEDs/srcfolder within Xilinx SDK. Choose to copy these source files into the project and click OK.

13.1) Make sure that the Zedboard is turned on and connected to the host PC with the provided micro USB cable.

In the quick selection tool bar, you will find a symbol with a red arrow and three green square boxes.

单击此符号以打开程序FPGA窗口。

Make sure that theHardware Platform被选为system_wrapper_hw_platform_0。

In the software configuration box, underELF File to Initialize in Block内存column, the row option must readbootloop。If not, click on the row and selectbootloop。

Now click on Program.

14.1) After the FPGA has been successfully programmed with the bit file, from theProject Explorer面板，右键单击“DigiLEDs”项目文件夹。去“Run As”and select“Launch on Hardware (System Debugger)“



Your Zedboard will then start the DigiLEDs Demo. Pressing Button 0 will cycle through three patterns on the RGB引领strip.