Getting Started with Digilent Pmod IPs

Digilent提供了几种旨在使FPGA上实现和使用PMOD尽可能直接的IP。本指南将描述如何在Vivado Microblaze或Zynq设计中使用PMOD IP核心。

At the end of this tutorial you will have a Vivado design and demo for your FPGA or Zynq platform that uses a Digilent Pmod IP core.

The following two dropdown tables show which Digilent FPGA system boards and Pmods are supported by this tutorial, as well as some details about each one that you will need to know to complete this tutorial.

支持平台

Platform	处理器类型
Arty A7	微型闪电
Arty S7	微型闪电
Arty Z7	Zynq
Basys3	微型闪电
CMOD A7	微型闪电
Cmod S7	微型闪电
Cora Z7	Zynq
Genesys2	微型闪电
Nexys4	微型闪电
nexys4-ddr	微型闪电
Nexys Video	微型闪电
Sword	微型闪电
Zybo	Zynq
ZyboZ7	Zynq

Pmods Supported

Pmod	Interface Type	Reference clock frequency (MHz)	参考时钟信号名称	中断引脚名称/s	Uses PmodGPIO	补充说明
8ld	GPIO	-	-	-	Yes	-
ACL	spi	80	ext_spi_clk	-	-	-
ACL2	spi	50	ext_spi_clk	-	-	-
AD1	spi	-	-	-	-	-
AD2	IIC	-	-	-	-	-
AD5	spi	50	-	-	-	-
ALS	spi	50	ext_spi_clk	-	-	-
AMP2	GPIO	-	-	timer_interrupt	-	-
aqs	IIC	-	-	-	-	-
BB	GPIO	-	-	-	Yes	-
ble	uart	-	-	-	-	-
BT2	uart	-	-	-	-	-
BTN	GPIO	-	-	-	Yes	-
能够	spi	100	ext_spi_clk	spi_打断GPIO_打断		-
CLS	spi	50	ext_spi_clk	-	-	-
CMPS2	IIC	-	-	-	-	SDK项目需要数学库
COLOR	IIC	-	-	-	-	-
DA1	spi	50	ext_spi_clk	-	-	-
DHB1	pwm/GPIO	-	-	-	-	-
DPG1	spi	50	ext_spi_clk	-	-	-
ENC	GPIO	-	-	-	-	-
ESP32	uart	-	-	-	-	-
GPS	uart	-	-	gps_uart_interrupt	-	-
GYRO	spi	50	ext_spi_clk	-	-	-
Hygro	IIC	-	-	-	-	-
JSTK	spi	16	ext_spi_clk	-	-	-
JSTK2	spi	16	ext_spi_clk	-	-	-
KYPD	GPIO	-	-	-	-	-
引领	GPIO	-	-	-	Yes	-
麦克斯森	GPIO	-	-	-	-	-
microSD	使用PMOD SD IP核心					-
MTDS	spi	-	-	-	-	-
NAV	spi/GPIO	50	ext_spi_clk	-	-	-
OLED	spi/GPIO	-	-	-	-	-
OLEDrgb	spi/GPIO	50	ext_spi_clk	-	-	-
皮尔	GPIO	-	-	-	-	-
R2R	GPIO	-	-	-	-	-
RTCC	IIC	-	-	-	-	-
SD	spi	-	-	-	-	-
SF3	spi	50	ext_spi_clk	qspi_interrupt	-	-
SSR	GPIO	-	-	-	Yes	-
SWT	GPIO	-	-	-	Yes	-
TC1	spi	50	ext_spi_clk	-	-
tmp3	IIC	-	-	-	-
WIFI	spi	-	-	wf_interrupt	-	Need 385 KB of BRAM or DDR

• Supported Digilent 7-Series FPGA System Board
• MicroUSB Cable/s
• One or More Supported Digilent Pmods

• Xilinx Vivado 2018.2 with Xilinx SDK and Digilent Board Files
  • Other versions of Vivado may work, but functionality is not guaranteed
  • 看到"Installing Vivado and Digilent Board Files"tutorial for more information.
• 数字Vivado IP Library
  • 第2步本教程涵盖了如何下载和提取这些文件。

要确定您是否需要使用Microblaze或Zynq进行本教程，请参阅该条目支持平台dropdown table found in theOverview Section本教程。或者，导航到您的平台资源中心这里。

微型闪电

跟着Getting Started with Vivado IP Integratortutorial to obtain a basic MicroBlaze block design.



An example of a MicroBlaze block design for a board that has external DDR memory.

Zynq

跟着Getting Started with Vivado IP Integratortutorial to obtain a basic Zynq block design.



Zynq块设计的示例。

2.1）找到Digilent的最新版本Vivado-libraryrepository where the version number matches the version of Vivado being used (example: “v2016.4-1” is the first release for Vivado 2016.4). Download theVivado-library-.zipfile (不是源代码档案之一！），然后在令人难忘的位置提取此存档。该GITHUB存储库包含大量旨在与Digilent板一起使用的IP内核，包括Digilent的所有PMOD IP内核和PMOD接口描述。

2.2）单击Project Settingsunder Project Manager.

2.3) ClickIP然后打开Repository Managertab. Click the Addbutton and select theVivado-library从邮政库中提取到的文件夹。点击好的。

3.1) Click theBoardtab (Highlighted in orange below)

3.2）向下滚动到板组件的PMOD部分。双击要设置的连接器。

3.3）为您的特定PMOD选择PMOD IP，然后单击好的。The photo below shows the IP core for PmodOLEDrgb being selected.

4.1）单击运行连接自动化then check the box next to the name of your Pmod IP core and click好的。

将参考时钟附加到PMOD IP核心是不同的，具体取决于您使用的平台。选择最能描述您平台的选项卡（请在“Overview Sectionif you don't know).

Zynq

5.1）双击Zynq处理系统block to re-customize it. In the menu to the left, clickClock Configuration。扩展PL Fabric Clocksdrop down and check the first FCLK_CLK that is not already checked to activate it. Set the requested frequency to the frequency required for your Pmod. This frequency can be found in the Pmod compatibility chart in theOverview Section本教程。点击好的。

Tip

如果其中一个FCLK_CLK已经检查has a frequency that matches the frequency needed for your pmod, you may use that clock. It is possible to connect a single clock to multiple destinations.

5.2) Connect this new clock to the clock input on your Pmod IP Core. The name of the clock input for your Pmod IP core can be found in the Pmod compatibility chart in theOverview Section本教程。

MicroBlaze with MIG

5.1）双击mig_7series block to re-customize it. In the Xilinx Memory Interface Generator window, keep clickingNext直到你看到选择其他时钟(shown below). Click this box and select the frequency required for your Pmod or the closest available slower frequency. The required frequency can be found in the Pmod compatibility chart in theOverview Section本教程。

Tip

如果已经使用了另一个时钟，并且具有与PMOD所需的频率相匹配的频率，则可以使用该时钟。可以将单个时钟连接到多个目的地。如果是这种情况，您可以取消从MIG配置对话框中出发。

5.2) Keep clickingNext。When you reach the pin selection screen, click证实接着好的。Keep clickingNext。点击接受在许可协议屏幕上，然后继续点击Next。Once you've reached the end, clickGenerateto regenerate your MIG block with your additional clocks.

5.3) Connect this new clock to the clock input on your Pmod IP Core. The name of the clock input port for your Pmod IP core can be found in the Pmod compatibility chart in theOverview Section本教程。

无MIG的微型闪电

5.1）双击时钟向导IP块以重新定位它。在“自定义”对话框中，选择“输出时钟”选项卡。检查尚未检查以激活它的下一个时钟。将请求的输出频率设置为PMOD所需的频率。该频率可以在PMOD兼容性图表中找到Overview Section本教程。点击好的。

Tip

如果已经使用了另一个时钟，并且具有与PMOD所需的频率相匹配的频率，则可以使用该时钟。可以将单个时钟连接到多个目的地。

5.2) Connect this new clock to the clock input on your Pmod IP Core. The name of the clock input for your Pmod IP core can be found in the Pmod compatibility chart in theOverview Section本教程。

将PMOD IP核心中断连接到处理器是不同的，具体取决于您使用的平台。选择最能描述您平台的选项卡（请在“Overview Sectionif you don't know).

Zynq

6.1) If a port namedIRQ_F2PZynq处理系统块上不存在，请双击块以重新定制它。在左侧的菜单中，单击Interrupts。Check and then expand Fabric Interrupts, then expandPL-PS中断并选中IRQ_F2P旁边的框。

6.2) Add aconcatIPcore to the block design. Re-customize the concat block to make sure that the number of inputs matches the number of interrupts you need to connect to your Zynq Processor - probably only one. Click好的。

6.3）将您的PMOD IP Core的中断端口连接到输入端口，并将Concat的输出端口连接到ZYNQ处理系统的IRQ_F2P端口。

微型闪电

6.1) If your MicroBlaze block doesn't have an AXI Interrupt Controller connected to it's INTERRUPT port, add an AXI Interrupt controller to your block design. Manually connect the interrupt port of the axi_intc_0 to the INTERRUPT port of your MicroBlaze block. UseConnection Automation要将其AXI接口连接到系统的其余部分。

6.2) Add a Concat IP core to the block design. Re-customize the concat block to make sure that the number of inputs matches the number of interrupts you need to connect to your Microblaze Processor - probably only one. Click好的。

6.3）将您的PMOD IP Core的中断端口连接到输入端口，并将Concat的输出端口和Concat的输出端口intrport of your AXI Interrupt Controller.

7.1）单击 Regenerate Layout按钮重新排列您的块设计。

7.2) Select 证实Design。This will check for design and connection errors.

7.3）如果您已经为您的块设计创建了HDL包装器，则是董事会特定的一部分入门…tutorial, skip the remainder of this step. Otherwise, after the design validation step we will proceed with creating a HDL System Wrapper. Click on the来源tab and find your block design.

7.4) Right click on your block design and click创建HDL包装器。Let Vivado manage the wrapper and automatically update it and click好的。



这将在VHDL中创建一个顶部模块，并允许您生成一个Bitstream。

8.1) In the top toolbar in Vivado, click 生成bitstream。This can also be found in the流导航器panel on the left, under程序和调试。如果您尚未保存设计，则将获得提示来保存块设计。

8.2）BIT文件生成将开始。该工具将运行Synthesis和Implementation。两者都成功完成后，将创建位文件。您会在项目窗口的右上角找到合成和实现的状态栏。

这个过程可能需要5至60分钟depending on the computer Vivado is running on and the size of the target FPGA.

8.3）生成了Bitstream后，屏幕上将弹出消息提示。您不必为此演示打开实施的设计。只需单击取消。

9.1) At the top of the Vivado window, click文件→导出→导出硬件。检查框Include Bitstream和click好的。This will give Xilinx SDK all of the information it needs to know about the hardware design, as well as the files needed to program the hardware onto a target FPGA system board.



A new file directory will be created in the project directory underecho_server.SDK类似于Vivado硬件设计项目名称。另外两个文件，.sysdef和.hdf也创造了。这个步骤创建一个new SDK Workspace.

9.2) On the main toolbar, click文件→启动SDK。将两个下拉菜单作为默认<本地项目>和click好的。这将打开Xilinx SDK并导入导出的硬件。

The HW design specification and included IP blocks are displayed in the “system.hdf” file. Xilinx SDK is independent of Vivado, i.e. from this point, you can create your SW project in C/C++ on top of the exported HW design. If necessary, SDK can be launched directly with the .sdk folder in the main Vivado project directory as the workspace. From this point, if you need to go back to Vivado and make changes to the HW design, then it is recommended to close the SDK window and make the required HW design edits in Vivado. After this you must follow the sequence of saving design, allowing Vivado to regenerate the HDL wrapper, and generating a new bit file. This new bit file and modified hardware design must then be exported to SDK.

在Project Explorertab on the left, you can see the hardware platform project. The name of the hardware platform follows the name of the block design wrapper created in Vivado. This hardware platform has all the HW design definitions, IP interfaces that have been added, external output signal information and local memory address information.

The drivers for any Pmod IPs in the design can be found in the appropriate folder in the hardware platform, under/drivers。If you want to edit these drivers, use the versions found in the board support package project underlibsrc/。如果您确实修改了驱动程序，请记住，硬件的任何更改都会覆盖这些更改，以及任何使用Regenerate BSP Sources选项。

11.1）单击 新的下拉箭头并选择申请项目。



Give your project a name that has no empty spaces and clickNext。

11.2）选择空应用程序从模板列表中，单击好的。

You will see two new folders in theProject Explorer控制板。

• 您的应用程序项目包含所有二进制文件，.c和.h（标题）文件
• 您的项目的董事会支持包，其中包含您项目可能包含的驱动程序源文件

Our main working source folder also contains an important file shown here which is the “lscript.ld”. This is a Xilinx auto generated linker script file and includes information about memory addresses for different IP components of your block design, as well as the sizes of other memory regions.

扩展design_1_wrapper_platform_0文件夹。在drivers文件夹，您将找到您在设计中使用的PMOD列表。扩展PMOD…/示例文件夹并复制此处找到的所有文件project_name/src文件夹。

13.1) Make sure that your board is turned on and connected to the host PC with micro USB cables for UART and programming. On some boards, you will only need to connect a single PROG/UART port while on others you will need to connect your PC to two different ports typically named UART and PROG or JTAG. On the top toolbar, click the 程序FPGA按钮。一些板还将要求它们连接到单独的电源。

13.2) ClickProgramto program your FPGA with your hardware design.

14.1) The majority of demos require that you use a serial terminal on your PC to read messages printed by the demo. Settings for the terminal will vary depending on your board, but typically you will need to use a baud rate of 115200 or 9600, 8 bit data, no parity bit, and one stop bit. Zynq projects will use 115200 baud, while the baud rate for MicroBlaze projects will depend on the configuration of the Uartlite IP in Vivado.

14.2）选择您的应用程序项目，然后单击 运行为…按钮。选择Launch on Hardware (System Debugger)和click好的。

14.3）Xilinx SDK将在Main.C上运行该程序。查看示例主文件顶部的评论标头，以获取有关演示的功能以及任何其他设置要求的更多信息。